R
Rikard Bosnjakovic
- Jan 1, 1970
- 0
I've been sitting with this problem the whole afternoon, and I'm on the
verge giving up. I just can't seem to sort it out.
I'm constructing a small alarm with three inputs. Call them S1, S2 and MR
(the last one for "Master reset"). For the alarm to be triggered, MR must
be closed (to +V). As soon as it opens, everything should be aborted.
Logic table:
MR S1 S2 Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
I.e. MR(S1+S2), or (MR NAND S1) NAND (MR NAND S2) in simplified form.
When the three inputs are closed they all provide +V. As soon as any of
them breaks they provide GND (logic zero). S1 and S2 are the kind of
switch that recieves a short pulse, that is they are not kept steadily at
+V for a long time (0.5-2 secs perhaps). This is why the alarm did not
work when I first prototyped it with a NAND-circuit (74LS00). The alarm
itself did work, though, but as soon as S1 or S2 dropped their pulses from
+V to GND the alarm switched off.
To keep them steady at +V I therefore redesigned the circuit to use an
SR-latch (74LS249) instead, but somehow I have messed up my mind
completely. The system works in a simulator, but (ofcourse) not in reality.
The prototype looks like this:
VCC
+
|
|---|
| |
VCC .-. .-.
| | | | |
| | | | |
| '-' '-' .---.
| | | o------|S |
| | | | | |
|---o---o---|---|---|---o--|R |o---- Y1
MR | | | | '---'
_/ | | | |
/------o/ o---o-------o |
| S1 | | .---.
| _/ | ------|S |
o------o/ o-------o---/ | | |
| S2 '--|R |o---- Y2
| '---'
|
|
===
GND
Y1 and Y2 outputs are OR:ed and forwarded to the actual alarm. This makes
the alarm go off as soon as S1 (Y1) or S2 (Y2) is triggered, and MR is closed.
But unfortunately it does not work, and I have been sitting for almost 4
hours trying to solve the problem, but I just can't think straight anymore.
Why, where and what am I doing wrong?
verge giving up. I just can't seem to sort it out.
I'm constructing a small alarm with three inputs. Call them S1, S2 and MR
(the last one for "Master reset"). For the alarm to be triggered, MR must
be closed (to +V). As soon as it opens, everything should be aborted.
Logic table:
MR S1 S2 Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
I.e. MR(S1+S2), or (MR NAND S1) NAND (MR NAND S2) in simplified form.
When the three inputs are closed they all provide +V. As soon as any of
them breaks they provide GND (logic zero). S1 and S2 are the kind of
switch that recieves a short pulse, that is they are not kept steadily at
+V for a long time (0.5-2 secs perhaps). This is why the alarm did not
work when I first prototyped it with a NAND-circuit (74LS00). The alarm
itself did work, though, but as soon as S1 or S2 dropped their pulses from
+V to GND the alarm switched off.
To keep them steady at +V I therefore redesigned the circuit to use an
SR-latch (74LS249) instead, but somehow I have messed up my mind
completely. The system works in a simulator, but (ofcourse) not in reality.
The prototype looks like this:
VCC
+
|
|---|
| |
VCC .-. .-.
| | | | |
| | | | |
| '-' '-' .---.
| | | o------|S |
| | | | | |
|---o---o---|---|---|---o--|R |o---- Y1
MR | | | | '---'
_/ | | | |
/------o/ o---o-------o |
| S1 | | .---.
| _/ | ------|S |
o------o/ o-------o---/ | | |
| S2 '--|R |o---- Y2
| '---'
|
|
===
GND
Y1 and Y2 outputs are OR:ed and forwarded to the actual alarm. This makes
the alarm go off as soon as S1 (Y1) or S2 (Y2) is triggered, and MR is closed.
But unfortunately it does not work, and I have been sitting for almost 4
hours trying to solve the problem, but I just can't think straight anymore.
Why, where and what am I doing wrong?