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Problems with an SR-latch

Discussion in 'Electronic Basics' started by Rikard Bosnjakovic, Jan 19, 2006.

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  1. I've been sitting with this problem the whole afternoon, and I'm on the
    verge giving up. I just can't seem to sort it out.

    I'm constructing a small alarm with three inputs. Call them S1, S2 and MR
    (the last one for "Master reset"). For the alarm to be triggered, MR must
    be closed (to +V). As soon as it opens, everything should be aborted.

    Logic table:

    MR S1 S2 Y
    0 0 0 0
    0 0 1 0
    0 1 0 0
    0 1 1 0
    1 0 0 0
    1 0 1 1
    1 1 0 1
    1 1 1 1


    I.e. MR(S1+S2), or (MR NAND S1) NAND (MR NAND S2) in simplified form.

    When the three inputs are closed they all provide +V. As soon as any of
    them breaks they provide GND (logic zero). S1 and S2 are the kind of
    switch that recieves a short pulse, that is they are not kept steadily at
    +V for a long time (0.5-2 secs perhaps). This is why the alarm did not
    work when I first prototyped it with a NAND-circuit (74LS00). The alarm
    itself did work, though, but as soon as S1 or S2 dropped their pulses from
    +V to GND the alarm switched off.

    To keep them steady at +V I therefore redesigned the circuit to use an
    SR-latch (74LS249) instead, but somehow I have messed up my mind
    completely. The system works in a simulator, but (ofcourse) not in reality.

    The prototype looks like this:

    VCC
    +
    |
    |---|
    | |
    VCC .-. .-.
    | | | | |
    | | | | |
    | '-' '-' .---.
    | | | o------|S |
    | | | | | |
    |---o---o---|---|---|---o--|R |o---- Y1
    MR | | | | '---'
    _/ | | | |
    /------o/ o---o-------o |
    | S1 | | .---.
    | _/ | ------|S |
    o------o/ o-------o---/ | | |
    | S2 '--|R |o---- Y2
    | '---'
    |
    |
    ===
    GND


    Y1 and Y2 outputs are OR:ed and forwarded to the actual alarm. This makes
    the alarm go off as soon as S1 (Y1) or S2 (Y2) is triggered, and MR is closed.

    But unfortunately it does not work, and I have been sitting for almost 4
    hours trying to solve the problem, but I just can't think straight anymore.

    Why, where and what am I doing wrong?
     
  2. Update:

    It seems I forgot a pull up-resistor for MR. Opening MR makes R float.

    Also, if I let MR be open during power up, the latch works (almost) as it
    should. Y1 and Y2 behave correctly, so I guess the previous design was tweaky.

    Another problem did however arise, and that is with the new resistor it
    does not matter if MR is open or close, the latch never resets.
     
  3. Brian

    Brian Guest


    The resistor to "MR" should be going to ground, not be a pull-up resistor.
    The 74LS249 is not a RS device, it is a "BCD-TO-SEVEN-SEGMENT
    DECODERS/DRIVER".

    Brian
     
  4. Yes, that's two typos for me. I meant pull-down (it's connected from
    ground to between MR and R), and it's 74LS279, not 249.
     
  5. Brian

    Brian Guest


    When you open switch MR, have you measured what inputs R actually go down
    to? What size resistor are you using for the pull-down resistor?

    Brian
     
  6. Pooh Bear

    Pooh Bear Guest

    I suspect you need a 'power-on reset' to set the initial conditions.

    Graham
     
  7. Brian

    Brian Guest

    Also you say you or or-ing the outputs -- how are you doing this? Are you
    feeding them into an or-gate? I hope you are not tying them together?

    Brian
     

  8. Since TTL inputs source current, and act as a high when left
    unconnected, the usual practice is to connect the switch between the
    input and ground, and add a pull-up resistor to +5.

    If you use a pull-down resistor (and switch to +5), the resistor value
    must be fairly low to ensure that the input is actually pulled down to
    a Low level.
     
  9. John Fields

    John Fields Guest

    ---
    Dunno, but check this out:


    If that doesn't work, log on to alt.binaries.schematics electronic
    and look fot the same subect as this thread for a _guaranteed_
    (well...) solution. :)
     
  10. I don't have any AND-gates with inverted inputs so it didn't work well for
    me (I only have NAND-gates). If I use NAND, the circuit works except for
    that MR needs to be open for S1/S2 to behave correctly, and that's the
    opposite of how I want it.

    I can, ofcourse, switch the NAND-ic to a AND and invert all inputs myself.
     
  11. John Fields

    John Fields Guest

     
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