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Power supply bypassing, again

I think that if your consultant is treating power and ground planes like
tuned transmission lines, he's a lunatic.

Hope This Helps!
Rich

I don't know, but his "simulation" of what's required for our product
looks a lot like the example in the PDF. I wonder if I can have a
business model like that?
 
J

John Larkin

Jan 1, 1970
0
I think I found the basis for our consultant's love of different value
caps.

http://www.pa.msu.edu/hep/d0/ftp/ru...nformation/xilinx_xapp623_decoupling_caps.pdf

I wonder what you people think of this?


"Every capacitor has a narrow frequency band where it is effective as
a decoupling capacitor."

What a doofus. His example, top of page 8, says it all.

As I mentioned, we use three or four identical, 0.33 uF maybe, bypass
caps per FPGA per supply voltage, 9-12 caps total for a Spartan 3. It
always works.

John
 
"Every capacitor has a narrow frequency band where it is effective as
a decoupling capacitor."

What a doofus. His example, top of page 8, says it all.

Yup, I can't say I follow his logic. The effectiveness of a decoupling
cap also depends on the current required. Seems to me at least. If I
need 1A at 10MHz or 1mA at 10MHz, I'd guess the same value cap won't
be doing the same thing.
As I mentioned, we use three or four identical, 0.33 uF maybe, bypass
caps per FPGA per supply voltage, 9-12 caps total for a Spartan 3. It
always works.

John

Yes but I'd say that depends heavily on what you're trying to do with
the thing. If you're strictly in the "digital" domain I suppose it's
enough, but if you're looking at the outgoing waveforms of a LVDS
transmitter, surely the quality of the power supply is paramount.
Perhaps a "1" will always be seen as a "1" by a digital receiver
expecting the worst, but what if you're looking at it with a high-
bandwidth analog scope? Betcha the waveforms won't look the same
depending on the amount of power decoupling. This is our problem.
 
J

John Larkin

Jan 1, 1970
0
I don't know, but his "simulation" of what's required for our product
looks a lot like the example in the PDF. I wonder if I can have a
business model like that?

Look at Figure 7. It shows the six caps as having monotonically
greater impedances at 1 GHz, with huge differences, even though the
esl's aren't very different for the four ceramic caps. That is crazy.

An 0603 cap has an inductance that changes little with capacitance
value. So above the srf, the z's will be about the same, regardless of
value, converging at high frequencies. That's not what he shows.

Just use biggish 0603 caps, 0.33 uF maybe, and tight power/ground
planes. Four caps per supply maybe.

This lunatic is suggesting something like 150 capacitors PER FPGA. How
can you route around 300 (or 600!) vias? He should be committed to a
nice institution where he can get the help he needs.

John
 
Look at Figure 7. It shows the six caps as having monotonically
greater impedances at 1 GHz, with huge differences, even though the
esl's aren't very different for the four ceramic caps. That is crazy.
I don't like how he makes it look like it's the planes demanding the
current. He shows cute little current loops looping around the cap and
the plane... Shouldn't he also include the path in to the device doing
the actual demand? Include the bond wires and die? But that would blow
his idea out the door, since typically you can't really know what's
going on in there, therefore you can't get a ESL number.
An 0603 cap has an inductance that changes little with capacitance
value. So above the srf, the z's will be about the same, regardless of
value, converging at high frequencies. That's not what he shows.

Just use biggish 0603 caps, 0.33 uF maybe, and tight power/ground
planes. Four caps per supply maybe.

This lunatic is suggesting something like 150 capacitors PER FPGA. How
Yes.
can you route around 300 (or 600!) vias? He should be committed to a

I had to. Use 3.5/3 rules to route between vias. It wasn't such a big
deal.
nice institution where he can get the help he needs.

I've taken up kayaking. Since I'm mostly a cyclist, my legs get a rest
and I feel that I remove far more frustration by rowing, since my
upper body is comparatively weak so I feel it more. Plus I get to do
and see something different!
 
J

John Devereux

Jan 1, 1970
0
John Larkin said:
Look at Figure 7. It shows the six caps as having monotonically
greater impedances at 1 GHz, with huge differences, even though the
esl's aren't very different for the four ceramic caps. That is
crazy.

An 0603 cap has an inductance that changes little with capacitance
value. So above the srf, the z's will be about the same, regardless of
value, converging at high frequencies. That's not what he shows.


He's got that "quantity" column... I think each line is the *combined*
(parallel) impedance for each of e.g. 32 x 2n2, 16 x 22n, 8x220n,
etc. If you look at the intercepts on the left hand "inductance" axis,
and assume he means "impedance", then it works out about right.

I can sort of make sense of it if you assume his capacitance values
are the largest practical in each package. He is trying to build a
~1000uF capacitor that has ~0.01 ohm impedance over a wide frequency
range.
 
J

John Larkin

Jan 1, 1970
0
Yup, I can't say I follow his logic. The effectiveness of a decoupling
cap also depends on the current required. Seems to me at least. If I
need 1A at 10MHz or 1mA at 10MHz, I'd guess the same value cap won't
be doing the same thing.

Imagine that Zetacap Inc makes a 10 farad, 0603 ceramic cap. Its SRF
will be about 2 KHz. Is it useless as a bypass above that?

Yes but I'd say that depends heavily on what you're trying to do with
the thing. If you're strictly in the "digital" domain I suppose it's
enough, but if you're looking at the outgoing waveforms of a LVDS
transmitter, surely the quality of the power supply is paramount.
Perhaps a "1" will always be seen as a "1" by a digital receiver
expecting the worst, but what if you're looking at it with a high-
bandwidth analog scope? Betcha the waveforms won't look the same
depending on the amount of power decoupling. This is our problem.


We did one gadget that used a Xilinx FPGA, with our bypassing style.
One signal path goes in/out four passes. Net jitter on the final
outputs is below 30 ps RMS.

But if my competitors have to go to 10 layers and 3 mil traces and use
1000 caps per board, why should I object?

John
 
J

John Popelish

Jan 1, 1970
0
I don't like how he makes it look like it's the planes demanding the
current. He shows cute little current loops looping around the cap and
the plane... Shouldn't he also include the path in to the device doing
the actual demand? Include the bond wires and die? But that would blow
his idea out the door, since typically you can't really know what's
going on in there, therefore you can't get a ESL number.

This is exactly why I went through the exercise of trying to
come up with effective ways to layout bypass capacitors
feeding chip pads. This articles examples of isolated caps
tied just to planes is silly and pointless.
 
We did one gadget that used a Xilinx FPGA, with our bypassing style.
One signal path goes in/out four passes. Net jitter on the final
outputs is below 30 ps RMS.

At what bit rate? Can you divide that into random and deterministic
jitter numbers?
But if my competitors have to go to 10 layers and 3 mil traces and use
1000 caps per board, why should I object?

John

Because we can do 3 ps jitter? :) Relax, we're not competitors!
 
J

Joerg

Jan 1, 1970
0
I think I found the basis for our consultant's love of different value
caps.

http://www.pa.msu.edu/hep/d0/ftp/ru...nformation/xilinx_xapp623_decoupling_caps.pdf

I wonder what you people think of this?

Are you guys still simulating that stuff? Seriously, I'd stop that and
get the layout rolling. Much of that staggered cap stuff is voodoo.
Doubling everytime you go to the next value down etc., oh man...

Yes, it can help to provide a 3300pF in parallel to a low cost 0.1uF cap
but that's about it IMHO.
 
J

John Larkin

Jan 1, 1970
0
At what bit rate? Can you divide that into random and deterministic
jitter numbers?

It was mostly deterministic, in the sense that one clock was clearly
modulating the prop delay of the timing paths that run on a completely
different clock.
Because we can do 3 ps jitter? :) Relax, we're not competitors!

3 ps with ECL is easy. CMOS is trickier, if only because Vcc modulates
prop delay.

John
 
J

John Larkin

Jan 1, 1970
0
For an opposing view see the following:
www94.web.cern.ch/HSI/s-link/devices/g-ldc/decouple.pdf

That is getting closer to reality, but it still ignores the elephant
in the kitchen, namely the planes themselves.

John
 
That is getting closer to reality, but it still ignores the elephant
in the kitchen, namely the planes themselves.

John

Well the planes are full of holes (literally) once you add the vias
for the Xilinx approach, which IMHO makes them less ideal and less
negligeable.
 
J

Joerg

Jan 1, 1970
0
Well the planes are full of holes (literally) once you add the vias
for the Xilinx approach, which IMHO makes them less ideal and less
negligeable.

ROFL! Great. Almost like some "modern" software. You fire up the
greatest of all programs only to find out that it didn't leave enough
RAM to do anthing with it.

Anyhow, heck, I'd just lay the thing out and see what shakes out.
Probably you could have had several layouts done for the time and money
that went into this whole study.
 
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