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Power-On Reset

Discussion in 'Electronic Design' started by Jim Thompson, Feb 9, 2005.

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  1. Ken Smith

    Ken Smith Guest

    I assume that these people were the same ones who would do this work.

    By any chance do you work for Maxim?

    There are quite a few chips (such as comparitors) that are well
    characterized at low voltages.

    You can often power parts of the reset circuit from the input side of the
    regulator to ensure that it gets powered before Vcc appears.

    If you want to be very sure of the Reset/ staying low during the supply
    upswing, you can use a JFET as the output switch.

    Some micro controllers have the reset circuit built in. If you follow the
    manufactures recomendations on most of those, the results are correct.

    The best and easiest way to do a brown out protection is to have the brown
    out comparitor turn off the main power. If the Vcc regulator is broken or
    the batteries too dead, this is the best thing to do. Running correct
    code to some random point and then restarting it over and over is no
    better than running bogus code.


    Funny you didn't include the power switch bounce case and the brown out
    case in your suggested checks. These are more likely in real life.
     
  2. If you ever had to troubleshoot equipment built that way you would
    never ask that question. The VTR interfaces for a video editing system
    at WACX in Orlando was designed for a reset generator chip, then they
    left out the chip and used a crappy R/C reset. The equipment worked
    when it was new but a couple years later it would only reset one out of
    20 or more attempts. You could play around with the R/C values and make
    it work for a couple weeks, but they finally agreed to let me mod the
    equipment by stuffing the missing parts on the board and eliminated the
    problems.
     
  3. Jim Thompson

    Jim Thompson Guest

    Absolutely not, that's why I was asking.
    I'm at the device level.

    I've found a solution I can't divulge at the moment, maybe in two
    years, that tracks process corners and times relative to what needs
    the reset.

    ...Jim Thompson
     
  4. Ken Smith

    Ken Smith Guest

    Actually, a good one will hold reset until a number of cycles of the
    system clock have gone by. Many parts must be clocked to reset correctly.
     
  5. Ken Smith

    Ken Smith Guest

    Add a clock monitor input so that you are sure that the system clock is
    running before you drop the reset.

    I assume you are using a MEMS relay and dashpot so adding a stepper relay
    shouldn't be too hard.
     
  6. Jim Thompson

    Jim Thompson Guest

    ROTFLMAO ;-)

    ...Jim Thompson
     
  7. In my experience, ASICs that need reset to be active for a number of
    clocks will have logic to implement that function internally. The
    external reset signal will asynchronously reset two or three flip
    flops which are usually arranged as a shift register, and the output
    of this shift register is the synchronous reset for the rest of the
    chip.
    Even going back a quarter century, the Intel 8284 clock generator (for
    the 8086) had logic to synchronise the reset to the system clock and
    provide minimum pulse widths, etc.

    I can't help feeling that a reset chip that's designed on some analog
    process ('cause it needs accurate comparators and a reference) won't
    be very good at handling a system clock that's the better part of a
    GHz (as they are on my boards).


    If you have any counter-examples, please list them. I'm always
    willing to learn.

    Regards,
    Allan
     
  8. Paul Rako

    Paul Rako Guest

    Well the funniest post was one suggesting that I work at Maxim,
    seeing as how I just spent over 3 years at National Semi and that
    I consider Maxim to be a despicable company (although they
    do have a few nice parts, if you can get ever get them).

    I guess I was trying to say that the existence of an entire
    product line at Maxim suggests this function is one worth paying
    for. The fellow who posted (correctly) that I didn't even mention
    switch bounce was right on the money as to why a cap and resistor
    can get you into trouble. Of course if the chip at least has POR
    circuitry and a POR reset pin then the cap and resistor may be fine,
    as long as the datasheet says so.

    Similarly I was not very clear about the process used-- I never meant
    to say you need an analog process. I am just saying the circuit needs
    to be designed at the transistor level. Digital simulators can
    be as simple as on/off indication with a little timing thrown in. That
    just is not enough when the power rails are all over that place. No,
    there are plenty of fine POR circuits done in CMOS for digital.

    If JT has a circuit that he can vary process corners it looks like he
    understands the grief of doing a POR. I have worked with a lot of
    digital guys that just can't comprehend that gate-level SPICE just
    does not work when the rails are at 1.7 volts. Heck, Bob Pease would
    say that analog SPICE doesn't work much better (;^o)-

    Hot-swap circuits are equally non-trivial. Did the card get stuck
    in for a millisecond, then yanked out, then stuck back in-- what is
    the state of all the circuits on both the mother and daughtercard..
    ect ect ect

    Paul
     
  9. Jim Thompson

    Jim Thompson Guest

    On Tue, 22 Feb 2005 16:57:16 GMT, Paul Rako

    [snip]
    I've been thru MUCH grief in my design lifetime, that's why I'm
    cautious as hell.
    Digital guys are amusing, aren't they ?:)
    I think Bob is becoming over-exaggerative in his old age. Picks
    absurd examples. Must be running out of material for his column.

    (Of course I'm a young man compared to Bob. He graduated MIT in 1961,
    I graduated MIT in 1962 :)
    [snip]

    My application isn't hot-swap, but it's similar... even has a
    charge-pump, which turned out to be helpful in making the POR timing
    ;-)

    ...Jim Thompson
     
  10. Ken Smith

    Ken Smith Guest

    I guess you don't use the 8051. The Philips ones are he one example I can
    think of straight off the top where the reset must be held for N clock
    cycles. The Atmel ones seem to take it a step further. They get messed
    up if the reset double pulses on the assert edge. I think that must be
    something to do with the ISP functions.
    So there's another example of a reset that needed to be held and synced.
    The fact that Intel provided the function on an external chip says
    something, I'm not sure what, about doing it inside the micro.
     
  11. I guess we are (but the bank and the boss enjoy the humor). At least
    my stuff goes *poof* with the rails at 1.7V, so using spice isn't all
    that interesting at 1.7V. ;-)
    Does your charge-pump operate with 1.7V rails? ;-) .25V?
     
  12. I have used 8051 variants in a number of products. They've always
    worked because the reset generator had a minimum pulse width that is
    greater than the oscillator start time.

    I take your point though: in an 8051 based design, it might be a good
    thing to keep it in reset until the oscillator starts, in case the
    crystal has unusual parameters and takes a long time to start.

    How would one go about making a 'crystal start' detector for an 8051?
    We don't want to load either of the xtal pins, and (IIRC) outputs like
    ALE won't be toggling while the reset is active.
    I think it says that in the days when 16000 transistors was a big
    chip, you should move as much stuff as possible off board. :)

    Regards,
    Allan
     
  13. Jim Thompson

    Jim Thompson Guest

    The specification requires 1.65V <= VDD <= 5.5V, over process corners
    and -40°C to +105°C

    I PASS ;-)

    ...Jim Thompson
     
  14. Rich Grise

    Rich Grise Guest

    .
    Why, thank you, Jim. That's one of the nicest things I've seen you
    write about me (and my kind ;-) ) in quite some time. :)

    Cheers!
    Rich
     
  15. Rich Grise

    Rich Grise Guest

    Don't dislocate your shoulder. ;-p

    Cheers!
    Rich
     
  16. Rich Grise

    Rich Grise Guest

    At the time, I was entirely serious. A cap and 10K pullup works just
    fine on, say, a 6502. I've been perusing the thread, and am slowly being
    dragged kicking and screaming into the 21st century. ;-)

    Thanks!
    Rich
     
  17. Ken Smith

    Ken Smith Guest

    Many FPGA and CPLD circuits do not become sane until the supply voltage
    reaches and stays above some voltage. It would be nice if the power on
    reset chips also could be used to force the SELF-DESTRUCT signal to ground
    and the EXPLODE-IN-FLAMES/ signal near Vcc until after the RESET is over
    and then glitch free connect them to the signals from the CPLD.
     
  18. Rich Grise

    Rich Grise Guest

    It says that Intel was staffed by idiots, or people who were so anxious
    to get _something_ working, that they jumped on the first design that
    actually shuttled data around, damn the clocking - full steam ahead!

    Thanks,
    Rich
     
  19. Rich Grise

    Rich Grise Guest

    But notice the operative phrase here - "designed for a reset generator
    chip". That particular chip does, in fact, need a proper reset, as has
    been covered in other posts in the thread.

    I was talking about the kinds of chips that they made in the '80s, where
    there was a pin specifically designed to take a cap and R, and has a
    Schmitt trigger, and the whole chip is designed to get reset by that
    little circuit.

    But, as I've said in another post, I'm slowly being dragged, kicking and
    screaming, into the 21st century. ;-)

    Speaking of which, there was a family of "reset generator" chips once -
    did they fade away too?

    Thanks!
    Rich
     
  20. Ken Smith

    Ken Smith Guest

    I wasn't using the 8051's oscillator in the case where it was an issue.

    I just did the RESET logic inside a CPLD. It worked ok. Normally, the
    8051s RC reset works fine.

    You can load the osc-out pin of the 8051 with a CMOS gate without causing
    serious trouble. CMOS gates have less capacitance than you normally hook
    to that node.

    OR: It says that the CPU designer screwed up and they didn't want to turn
    the mask again.

    The 8080 had an instruction that was an almost 16 bit subtract. It didn't
    borrow correctly. I suspect that they changed the data sheet rather than
    fix a broken subtract.
     
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