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Power-On Reset

Discussion in 'Electronic Design' started by Jim Thompson, Feb 9, 2005.

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  1. Jim Thompson

    Jim Thompson Guest

    I need a power-on reset that lasts around 5ms.

    Process is CMOS

    1.65V < VDD < 5.5V

    Components available besides CMOS:

    Lateral PNP
    Vertical PNP
    Caps up to 20pF
    Resistors up to 1Meg

    Suggestions?

    ...Jim Thompson
     
  2. Tim Shoppa

    Tim Shoppa Guest

    Suggestions?

    Many of the recent Microchip PIC power-on-resets use a digital counter
    internally. I'm guessing that they're working within confines similar
    to what you have and also they're trying to keep power consumption
    while asleep to a minimum and deal with brownout recovery. I don't
    know the details but they must be taking on-chip clock in the 10's or
    100's of kHz to tick everything along.

    What requirements do you have regarding power consumption while asleep,
    brownout recovery, ?

    Tim.
     
  3. Your favorite oscillator and a 20 bit counter. In the meantime you can
    continue work on that cap multiplier.
    Cheers,
    Harry
     
  4. John Larkin

    John Larkin Guest


    Why not just hold reset true as long as Vcc is below some level?

    John
     
  5. Jim Thompson

    Jim Thompson Guest

    I need to time-out long enough that a charge-pump has reached maximum.

    Charge-pump is regulated by controlling input, has no load other than
    capacitance, so I can't sense CP voltage without disturbing things.

    ...Jim Thompson
     
  6. Jim Thompson

    Jim Thompson Guest

    This dude doesn't sleep, but power consumption is critical.

    (Hearing-aid-related is all I can say right now.)

    ...Jim Thompson
     
  7. 50KHz relaxation osc, 8 bit counter, flip flop?

    There was an experimental thread here last year on
    CMOS flip flops that indicated that they could be
    'guided' into the required POR state by pull up/down
    R's. That could maybe be the way to bring up the counter
    and flip flop in the Reset state.
     
  8. There are a lot of parts built in CMOS that do this, but very little
    on how they do it internally. Here's one (first made by Microchip or
    perhaps some company they bought):

    http://www.national.com/ds/MC/MCP809.pdf
    http://ww1.microchip.com/downloads/en/DeviceDoc/11194c.pdf

    It's basically what you want, except with a 200ms delay.

    In Microchips' block diagram they show a bandgap reference, a
    comparator and a delay circuit, just as you might expect.

    Similar non-stand-alone functions that people have designed into chips
    tend to be inferior to parts such as the above. Hopefully you can do
    better!


    Best regards,
    Spehro Pefhany
     
  9. Guest

    Similar non-stand-alone functions that people have
    I think that battery-operated consumer single-chip gizmos were using a
    similar (although probably no band-gap) technique back into the early
    80's. At least that was the only way I could figure they were
    generating a power-on-reset delay of hundreds of ms. Some of these
    worked down below 1.2V. I never did figure out what magic they used
    internally (maybe related to, or even exactly the same as, Jim's
    mention of an internal charge pump?)

    Tim.
     
  10. Guest

    Similar non-stand-alone functions that people have
    I think that battery-operated consumer single-chip gizmos were using a
    similar (although probably no band-gap) technique back into the early
    80's. At least that was the only way I could figure they were
    generating a power-on-reset delay of hundreds of ms. Some of these
    worked down below 1.2V. I never did figure out what magic they used
    internally (maybe related to, or even exactly the same as, Jim's
    mention of an internal charge pump?)

    Tim.
     
  11. Joerg

    Joerg Guest

    Hello Harry,
    That is how I would do it, similar to a CD4060.

    It may not need 20 bits. That would depend on the trade-off between die
    area per pF for the oscillator capacitor and the real estate each
    divider occupies. It also depends on how small a current can safely be
    generated and used to charge and discharge that cap. 20pF seems pretty
    fat for a chip.

    Jim, maybe you can instead incorporate some nifty logic that holds down
    the reset until the charge pump has reached the desired voltage level,
    like x times battery level.

    Regards, Joerg
     
  12. Jim Thompson

    Jim Thompson Guest

    I don't want to sense the CP output voltage. It's driving a
    capacitive transducer, and sensing will load it..

    ...Jim Thompson
     
  13. Joerg

    Joerg Guest

    Hello Jim,
    I don't know the architecture. But is there a way to sense and switch
    the divider path hi-Z when done sensing?

    Regards, Joerg
     
  14. Tim Wescott

    Tim Wescott Guest

    Even with a FET gate? Or is that a stupid question -- the closest I've
    been to IC design is that 4th-year class where you build an op-amp out
    of a CA3096 and a CA3086.
     
  15. Jim Thompson

    Jim Thompson Guest

    The highest voltage on-chip is the pump output, so a FET gate needs a
    drain supply.

    ...Jim Thompson
     
  16. Tim Wescott

    Tim Wescott Guest

    And to think I'm charging folks for my time today -- good thing it's
    something I already know how to do.

    So you're back to an RC oscillator and a counter?
     
  17. Jim Thompson

    Jim Thompson Guest

    I'm contemplating a second pump with smaller capacitors as a
    counter... something like "CP-Style-Counter.pdf" on the
    S.E.D/Schematics page of my website.

    Since it would be ratiometric with the main pump I can use a sensor
    that's below VDD and thus powerable.

    ...Jim Thompson
     
  18. Paul Rako

    Paul Rako Guest

    POR circuits are NOT trivial to design. Many people
    have crashed and burned using latches, 555 timers and
    other schemes. This is why Maxim can get 50 cents for
    a reset chip. I have been told by very smart people that
    the only valid approach to a POR circuit is a transistor-
    level approach. You have to have fully characterized
    transistor models if you expect to SPICE it, macromodels
    will not do. Be sure to exercise the circuit (reality preferred
    to SPICE) for very slow as well as very fast power turn-on and
    over a range of temperatures and loads. This is really a
    design challenge so don't take it lightly.
     
  19. Rich Grise

    Rich Grise Guest


    What's wrong with a 1 uF cap from the POR pin to ground, with,
    say, a 10K pullup?

    Thanks,
    Rich
     

  20. Rich, I am unable to tell whether you were being sarcastic, or whether
    you really don't know why an RC circuit is a bad reset generator (in
    general).


    Commonly encountered supply waveforms that don't produce a reliable
    reset from the RC circuit:

    1. A brief dip in the supply voltage that goes low enough to crash
    the processor, but it doesn't discharge the cap enough to cause a
    reset when the supply returns to normal.

    2. Very slow dv/dt. The RC circuit will not assert reset.

    3. The supply voltage sitting in a "brownout" state indefinitely.
    The RC circuit will not assert reset.


    A good reset generator will hold reset active for all values of supply
    voltage below some threshold all the way down to zero volts,
    regardless of dv/dt (except maybe for glitch filtering), and keep
    reset active for a certain period (some tens to hundreds of ms) after
    the voltage goes above the threshold.


    Regards,
    Allan
     
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