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Power ON reset in FPGA

Discussion in 'Electronic Design' started by [email protected], Sep 30, 2005.

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  1. Guest

    Hi all,

    I have a question on POR(Power on reset generation ) using FPGA.
    My FPGA does not have a external Power ON reset , i am planning to
    generate a Power ON reset in the FPGA only.Is it really feasible to
    do this in an FPGA, and use this as the reset for my logic.
    Any suggestions appreciated??

  2. Which FPGA? SRAM based FPGAs need the be configured, which will put them in
    the state your design calls for. It isn't a good idea to rely on this as a
    "reset" though, because subsequent resets will require a reconfiguration.
    There are usually global resources tied to an I/O to do the reset (resets are a
    whole kettle of fish).
  3. Joerg

    Joerg Guest

    Hello Praveen,
    I couldn't sleep well if I had ever done that. External resets aren't
    that difficult. Even an RC plus Schmitt trigger, anything would be
    better than relying on internal paths for POR, IMHO.

    Also you generally have to think about brownout resets (BOR) as well, in
    case your power supply goes down for just a brief moment. Enough to
    cause hang-ups but maybe not enough to trigger a regular POR.

    You can also buy chips for that. Some come with a nice watchdog feature.

    Regards, Joerg
  4. Mac

    Mac Guest

    I'm not clear on exactly what you are asking.

    Depending on the type of FPGA you use, there is a period of time after the
    FPGA gets powered up when your design is not yet loaded. The reset needs
    of the FPGA prior to and during this time should be documented in the

    Once your bitstream is loaded (if it is that type of FPGA), I would think
    you would want a good reset input, and would make sure that reset is
    asserted for a certain amount of time if the power dips or whatever.

    Any board complicated enough to use an FPGA should have engineered
    power-on sequencing.

  5. Stephane

    Stephane Guest

    external_asynchronous_reset or DLL_locked is a good reset.
    for large designs, avoid async global reset when possible.
    you might post on comp.arch.fpga
  6. PeteS

    PeteS Guest

    I think the OP might not understand one must provide a reset and
    declare it for the device

    So in the constraint file we might see something like

    NET "rst_l" LOC = "B8"; reset input

    and in the code

    module myfpga

    and in the code

    input rst_l; reset input, active low

    then for clarity we might see
    wire reset;

    assign reset = !rst_l;

    and eventually

    always @ (reset)
    begin something


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