power estimation with nanosim

[saida]

Hello ,
I am new worker in nanosim and i did a netlist in verilog to estimate the power for an inverter but the report of current and power measre 0 µw . can some one give me the reason for that . thank you

Node: gnd
Average current : 0.00000e+00 uA
RMS current : 0.00000e+00 uA

No current peaks noted.

Node: vdd
Average current : 0.00000e+00 uA
RMS current : 0.00000e+00 uA

No current peaks noted.

Node: in
Average current : 0.00000e+00 uA
RMS current : 0.00000e+00 uA

No current peaks noted.

Node: out
Average current : 0.00000e+00 uA
RMS current : 0.00000e+00 uA

 

[Harald Kapp]

The static power consumption of a single CMOS inverter is about 0W.
"No current peaks noted." indicates that you simulated DC conditions, no switching of the inverter.

As the power of a CMOS circuit is proportional to: P~f * C * V²,
you need to simulate the operation of the inverter at some comparatively high frequency (>1MHz). Also you may get better results by simulating thousands of inverters and dividingthe result by the number of inverters to arrive at the power dissipation of a single gate.

 

[saida]

thank you . I do a circuit with 4 inverter but it gives me the same result. i don't know what should i change.
there is the code that i do if you can help me

**inv.v : verilog code
module inv (a,b,c,d,e);
input a,b,c,d;
output e;
IVSVTX2 U3 ( .A(a), .Z(b) );
IVSVTX2 U4 ( .A(b), .Z(c) );
IVSVTX2 U5 ( .A(c), .Z(d) );
IVSVTX2 U6 ( .A(d), .Z(e) );

endmodule

**inv.vec simulation file

type vec
signal a b c d
radix 1111
io bbbb
0 1010
30 0101
60 1010
90 0101
105 1010

and those are the command to simulate
set_print_format for=out
set_print_format for=fsdb
use_sim_case l
print_node_v *
print_node_i vdd
print_probe_i avg *
print_node_logic *
report_block_powr total track_power=1 *
set_print_iwindow period=240ns start=629ns end=2000ns
print_probe_i avg *
set_sim_mode ud

 

[Harald Kapp]

I'm not familiar with verilog, but I think you're way off running the inverters at a few MHz.