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Power Dissipation Across A Transistor In Cutoff

Akshatha Venkatesh

Jan 14, 2017
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Vbe of 0.7 is not what you need to worry about. Remember that there are not just transistors. You need to use the minimum on voltage from the datasheet.

I didn't quite understand this. Would you please elaborate ?
How do I determine if the transistor T201a is in saturation or not ?
 

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How do I determine if the transistor T201a is in saturation or not ?

When the base collector junction is forward biased.

And since you know (roughly) what Vbe is (and that's NOT the voltage between the "base" and emitter terminals of this device, because you don't have access the the base directly), when Vce is less than this, the collector junction is forward biased.

These devices are not intended for analog use, their specifications leave unspecified what will happen where the input terminal has a voltage on it between the max OFF voltage and the min ON voltage. What happens between those voltages can probably be calculated, but I'm not sure with your level of experience that you're up to it. The large variation in the actual values of the internal resistors also means there is a significant amount of uncertainty in the current drawn at the "base" terminal (but not the voltage required). All up, it is better to use the values from the datasheet and indicate when the outputs are guaranteed to be in one of two states, and the voltage range where the outputs are uncertain.
 

Akshatha Venkatesh

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And since you know (roughly) what Vbe is (and that's NOT the voltage between the "base" and emitter terminals of this device, because you don't have access the the base directly), when Vce is less than this, the collector junction is forward biased.

These devices are not intended for analog use, their specifications leave unspecified what will happen where the input terminal has a voltage on it between the max OFF voltage and the min ON voltage. What happens between those voltages can probably be calculated, but I'm not sure with your level of experience that you're up to it. The large variation in the actual values of the internal resistors also means there is a significant amount of uncertainty in the current drawn at the "base" terminal (but not the voltage required). All up, it is better to use the values from the datasheet and indicate when the outputs are guaranteed to be in one of two states, and the voltage range where the outputs are uncertain.


Ok you say that it is better to use the values from the datasheet . What values ? I don't completely understand how to read a datasheet, please help.
Thank You
 

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The on voltage and the off voltage. We've been through this before.
 

Akshatha Venkatesh

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The on voltage and the off voltage. We've been through this before.
does "turn on" and "fully turn on" mean the same ? I know there's difference between the active region and the saturation region, but in this scenario , I should be only concerned with the saturation and cutoff region, right ?
 

Arouse1973

Adam
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does "turn on" and "fully turn on" mean the same ? I know there's difference between the active region and the saturation region, but in this scenario , I should be only concerned with the saturation and cutoff region, right ?

No it doesn't to me. Fully on would mean saturated in a BJT. Turn on I don't think has a place here.
Adam
 

Akshatha Venkatesh

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No it doesn't to me. Fully on would mean saturated in a BJT. Turn on I don't think has a place here.
Adam
So in the datasheet below, the "on voltage"refers to the "fully on" condition ? the saturation condition, is it ? and the "off voltage" refers to the cutoff condition ? Am I right or wrong ?
I'm sorry , I couldn't attach the whole datasheet since it was too large.
 

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The off voltage refers to the maximum voltage where the transistor is guaranteed to be off (the definition of off should be in the datasheet somewhere, but you can probably assume cutoff).

At voltages between the off and the on voltage it will go through the active region, however the exact voltage where it leaves cutoff and (transits the active region, then) enters saturation are not specified.

In any case, saturation is defined for a particular collector current. The datasheet assumes a 10mA collector current, but in your case (from memory) I think it's highly unlikely to exceed 1mA for that first transistor.

The circuit is probably simple enough to enter into a simulator fairly quickly and to compare the input to the outputs for a ramped input voltage. You may want to run this a couple of times varying the gain of the transistors and the values of the internal resistors to get an idea of how the variation due to component tolerances affects the circuit operation.

This is an almost perfect case for Monte Carlo simulation (where these values are automatically and randomly varied) but the number of degrees of freedom here (6) is small enough that you could vary them one at a time to see what effect each has, and maybe a couple of final runs with the values which will cause the most extreme behavior. This would give you some confidence of the envelope that a real implementation would likely fall into.
 

Akshatha Venkatesh

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The off voltage refers to the maximum voltage where the transistor is guaranteed to be off (the definition of off should be in the datasheet somewhere, but you can probably assume cutoff).

At voltages between the off and the on voltage it will go through the active region, however the exact voltage where it leaves cutoff and (transits the active region, then) enters saturation are not specified.

In any case, saturation is defined for a particular collector current. The datasheet assumes a 10mA collector current, but in your case (from memory) I think it's highly unlikely to exceed 1mA for that first transistor.

The circuit is probably simple enough to enter into a simulator fairly quickly and to compare the input to the outputs for a ramped input voltage. You may want to run this a couple of times varying the gain of the transistors and the values of the internal resistors to get an idea of how the variation due to component tolerances affects the circuit operation.

This is an almost perfect case for Monte Carlo simulation (where these values are automatically and randomly varied) but the number of degrees of freedom here (6) is small enough that you could vary them one at a time to see what effect each has, and maybe a couple of final runs with the values which will cause the most extreme behavior. This would give you some confidence of the envelope that a real implementation would likely fall into.

which simulator would you suggest ?
And the On State Voltage for the first transistor is 2.5 V (min) , and this voltage is across the emitter ??
But shouldn't the emitter voltage and collector voltage be more than 5V(base volatge) , for the first transistor to be in saturation ?
 
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Well you could probably try the online falstad circuit simulator. It's not particularly fast or powerful, but it might do.

If the on state voltage is 2.5V, then for an NPN version of these devices, the input terminal (loosely the base) must be 2.5 volts more positive than the emitter. The collector voltage doesn't some into this.

If this results in the internal transistor becoming saturated then it will be 0.7 volts (or less) more positive than the emitter.
 

Akshatha Venkatesh

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Well you could probably try the online falstad circuit simulator. It's not particularly fast or powerful, but it might do.

If the on state voltage is 2.5V, then for an NPN version of these devices, the input terminal (loosely the base) must be 2.5 volts more positive than the emitter. The collector voltage doesn't some into this.

If this results in the internal transistor becoming saturated then it will be 0.7 volts (or less) more positive than the emitter.
But as you can see in the circuit , the input terminal (base) has a fixed voltage of 5 v.
 

Akshatha Venkatesh

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The off voltage refers to the maximum voltage where the transistor is guaranteed to be off (the definition of off should be in the datasheet somewhere, but you can probably assume cutoff).

At voltages between the off and the on voltage it will go through the active region, however the exact voltage where it leaves cutoff and (transits the active region, then) enters saturation are not specified.

In any case, saturation is defined for a particular collector current. The datasheet assumes a 10mA collector current, but in your case (from memory) I think it's highly unlikely to exceed 1mA for that first transistor.

The circuit is probably simple enough to enter into a simulator fairly quickly and to compare the input to the outputs for a ramped input voltage. You may want to run this a couple of times varying the gain of the transistors and the values of the internal resistors to get an idea of how the variation due to component tolerances affects the circuit operation.

This is an almost perfect case for Monte Carlo simulation (where these values are automatically and randomly varied) but the number of degrees of freedom here (6) is small enough that you could vary them one at a time to see what effect each has, and maybe a couple of final runs with the values which will cause the most extreme behavior. This would give you some confidence of the envelope that a real implementation would likely fall into.
How are you saying that it is highly unlikely to exceed 1mA for the first transistor ?
 

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Assume Vce(sat) is 0V and that the other two transistor's input pin is equivalent to their base resistor to ground.

Those conditions lead to a slight overestimate

This calculation of current is trivial and I would be profoundly disappointed if you can't do it.
 

Akshatha Venkatesh

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Assume Vce(sat) is 0V and that the other two transistor's input pin is equivalent to their base resistor to ground.

Those conditions lead to a slight overestimate

This calculation of current is trivial and I would be profoundly disappointed if you can't do it.
Can you please help me with the pnp part of the circuit for the question i have asked above ?
 
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