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PMOS Current Mirror

Discussion in 'General Electronics Discussion' started by Alex_Bam, Oct 7, 2020.

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  1. Alex_Bam


    Sep 28, 2020
    I am designing a PMOS current mirror in 350nm Cadence technology [attached].
    Problem: keeping the dimension (W/L ratio) of both the PMOS transistors constant, I should get mirrored current the same as the reference current (according to mirror circuit principle). But I am not getting the same current as reference current. e.g.
    -When my reference current is 10uA then the mirror current is 16.6uA with 5V supply voltage (Vdd)

    When I change the supply voltage then the mirror current started getting better as e.g.
    - reference current 10uA then the mirror current is 13.4uA with 3.3V supply voltage (Vdd).
    -reference current 10uA then the mirror current is 10.3uA with 1.8V supply voltage (Vdd).

    Dimension of MPO: W/L=10u/0.5u
    Dimension of MP1: W/L=10u/0.5u

    Alex Current mirror invert.JPG

    I would like to know How and Why my mirror current is changing with changing supply voltage (Vdd)?

    Moderatores note : inverted colors for better readability and posted inline

    Attached Files:

    Last edited by a moderator: Oct 7, 2020
  2. Harald Kapp

    Harald Kapp Moderator Moderator

    Nov 17, 2011
    It's been quite some time I had to delve into MOSFET physics, but I think your issue is due to non-ideal behavior of the MOSFETs leading to a finite output resistance of the current source. See this Wikipedia article, namely the part "output resistance" where it shows how output resistance depends on channel length modulation which becomes increasingly pronounced with shorter channels (0.5 µm!).
    If possible, try to test the setup with a MOSFETR model having a much longer channel.

    One way out of this might be using a cascode current mirror circuit.
    Alex_Bam likes this.
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