PLL with very high feedback clock and reference clock dividers

[bender]

I am trying to design a Charge pump PLL with very high feedback and
reference dividers (around 2^15). The input clock is about 150 Mhz but
the output clock will be from 10-150 Mhz. If both N & M (dividers)
values are around 30,000, the Phase detector checks the edges every
220 uS, i.e. the output pulse width is in the order 200uS when the PLL
starts (Nanosim simulation).Since the output of the Charge pump + LPF
depends on the width of the output at Phase detector, the Vcontrol
(LPF output), varies very high at every edge that the VCO fails to
lock.

So far, I’ve been only considering altering a standard CP PLL
(designed to work with no dividers) to work for this. Should I be
considering other options such as fraction N PLL or maybe different
PLL type? Can a CP PLL work with high values at both the dividers
Note: . I haven’t been able to find any information on desiging very
high divider value PLL from books or internet searches.
The closest PLL I have come across that uses very high divider values
are for cellular transceivers which uses 30,000 at feedback clock
divider but no reference clock divider.

 

[Andrew Holme]

I am trying to design a Charge pump PLL with very high feedback and
reference dividers (around 2^15). The input clock is about 150 Mhz but
the output clock will be from 10-150 Mhz. If both N & M (dividers)
values are around 30,000, the Phase detector checks the edges every
220 uS, i.e. the output pulse width is in the order 200uS when the PLL
starts (Nanosim simulation).Since the output of the Charge pump + LPF
depends on the width of the output at Phase detector, the Vcontrol
(LPF output), varies very high at every edge that the VCO fails to
lock.

So far, I’ve been only considering altering a standard CP PLL
(designed to work with no dividers) to work for this. Should I be
considering other options such as fraction N PLL or maybe different
PLL type? Can a CP PLL work with high values at both the dividers
Note: . I haven’t been able to find any information on desiging very
high divider value PLL from books or internet searches.
The closest PLL I have come across that uses very high divider values
are for cellular transceivers which uses 30,000 at feedback clock
divider but no reference clock divider.

Why are you aiming for such a low phase detector rate? Is it to get a small
channel spacing? Fractional-N would allow you to achieve even smaller
steps; but with a much higher PFD rate.

The problems with using such a low PFD rate are two-fold:

1. It forces you to use a very narrow loop bandwidth to attenuate reference
frequency spurs on the VCO output. This means slow lock time.

2. VCO phase noise inside the loop bandwidth will be 20*log10(30000) = +89.5
dB higher than PFD phase noise / jitter; however, this might not be an issue
if your loop bandwidth is only 10 Hz!

You're unlikely to find a VCO covering much more than a 2:1 frequency range,
so to cover 10 - 150 MHz will need a bank of switched VCOs. Or you could
generate the lower frequencies by dividing down the output of a high
frequency VCO.

Rgds,
Andrew.

 

[MooseFET]

I am trying to design a Charge pump PLL with very high feedback and
reference dividers (around 2^15). The input clock is about 150 Mhz but
the output clock will be from 10-150 Mhz.

If you are going that far all in one range you are forced to use an RC
sort of oscillator. You really need to break the range up. With a
range that large you have to have a high control voltage in to
frequency out gain in the VCO.

If both N & M (dividers)
values are around 30,000, the Phase detector checks the edges every
220 uS, i.e. the output pulse width is in the order 200uS when the PLL
starts (Nanosim simulation).Since the output of the Charge pump + LPF
depends on the width of the output at Phase detector, the Vcontrol
(LPF output), varies very high at every edge that the VCO fails to
lock.

You need to make the filter after the charge pump have a small enough
phase shift and a low enough gain that the closed loop is stable. The
system will go all over the place if you don't. If this is the sort
of "failed to lock" you see look at the filter.


If you don't need to do all the frequencies, you may want to change
both M and N and make their values smaller. This lets you do lots of
frequencies but not all in exact steps.

 

[[email protected]]

Thank you everyone.

I cannot really change the divider value because I don''t control it.
So i have to assume that an increased jitter and bandwidth limitation
are ok . I will look into Frequency synthesizers more and a more
stable filter as per your suggestions.

 

[Jan Panteltje]

If you are going that far all in one range you are forced to use an RC
sort of oscillator. You really need to break the range up. With a
range that large you have to have a high control voltage in to
frequency out gain in the VCO.

You can use a fixed 300 MHz and a variable 310 MHz and mix down.
Then you only need to tune a 310 - 460 MHz range.
The lowpass is then simple too.