PLL spurs

[Phil Hobbs]

Hello,

I am trying to understand how a particular vcxo-based pll works.
When using a spectrum analyzer to probe the oscillator part
of the circuit, I find spurs located at 44 kHz away from the
main frequency (say 200 MHz). These spurs are not present when
there is no input clock to lock on to, i.e. when the vcxo is
freely running; they are there only when the pll is locked
on the incoming clock. The PFD works at 1/4 the vcxo
frequency which is also the input clock frequency. So I cannot
understand where these spurs may be coming from?
Should this be a worry? I could imagine that these spurs
may under some conditions excite some spurious modes of the
crystal itself (unless they are actually exactly that, but they
do not seem to, since the crystals have been characterized beforehand
and there is no spurious mode at 44 kHz from the fundamental?)

Should I add that I have no experience whatsoever with this
sort of things...

Thanks,
Stefan Simion

Guess: you're running this off a switching power supply. When the PFD
is not running, its output is sitting low, and hence sees little or no
power supply noise. The oscillator has an internal supply filter or VR
to prevent its being pulled.

Cheers,

Phil Hobbs

 

[martin griffith]

Hello,

I am trying to understand how a particular vcxo-based pll works.
When using a spectrum analyzer to probe the oscillator part
of the circuit, I find spurs located at 44 kHz away from the
main frequency (say 200 MHz). These spurs are not present when
there is no input clock to lock on to, i.e. when the vcxo is
freely running; they are there only when the pll is locked
on the incoming clock. The PFD works at 1/4 the vcxo
frequency which is also the input clock frequency. So I cannot
understand where these spurs may be coming from?
Should this be a worry? I could imagine that these spurs
may under some conditions excite some spurious modes of the
crystal itself (unless they are actually exactly that, but they
do not seem to, since the crystals have been characterized beforehand
and there is no spurious mode at 44 kHz from the fundamental?)

Should I add that I have no experience whatsoever with this
sort of things...

Thanks,
Stefan Simion

Is there any digital audio in your system, one of the sampling
frequencies is 44.1KHz?

Just a long shot!


martin

Serious error.
All shortcuts have disappeared.
Screen. Mind. Both are blank.

 

[Stefan Simion]

Hello,

I am trying to understand how a particular vcxo-based pll works.
When using a spectrum analyzer to probe the oscillator part
of the circuit, I find spurs located at 44 kHz away from the
main frequency (say 200 MHz). These spurs are not present when
there is no input clock to lock on to, i.e. when the vcxo is
freely running; they are there only when the pll is locked
on the incoming clock. The PFD works at 1/4 the vcxo
frequency which is also the input clock frequency. So I cannot
understand where these spurs may be coming from?
Should this be a worry? I could imagine that these spurs
may under some conditions excite some spurious modes of the
crystal itself (unless they are actually exactly that, but they
do not seem to, since the crystals have been characterized beforehand
and there is no spurious mode at 44 kHz from the fundamental?)

Should I add that I have no experience whatsoever with this
sort of things...

Thanks,
Stefan Simion

 

[Stefan Simion]

I use a E3610A linear power supply and I am not aware of any 44.1 kHz
noise source nearby. In fact the spur freq. varies from one part to the
other, for example in another case it is ~60 kHz from the main freq.
This delta(f) is more or less "flat" when the input frequency is well within
the pll lock range; it starts to increase towards the upper end of the lock
range; and decreases towards the lower end.

 

[Tim Wescott]

I use a E3610A linear power supply and I am not aware of any 44.1 kHz
noise source nearby. In fact the spur freq. varies from one part to the
other, for example in another case it is ~60 kHz from the main freq.
This delta(f) is more or less "flat" when the input frequency is well within
the pll lock range; it starts to increase towards the upper end of the lock
range; and decreases towards the lower end.

Now _that_ sounds like your loop is unstable, or at least severely
underdamped, with an oscillation frequency that tracks the differential
gain of the vxco over it's frequency range.

What kind of loop filter are you using? Is it active? How many
integrators? Pole/zero positions, etc.? It may behoove you to take a
look at the frequency command to the vxco and see what kind of content
it has.

 

[Stefan Simion]

There are some other (more direct) indications that the loop
may be unstable, namely large jitter being introduced under
some conditions. It does not always happen though, and the
measurements I am referring to are done when everything seems
to be working fine.

I don't know the fine details of the loop design (this is an ASIC)
but from what I understand the intention was to have a single-pole
filter. In fact the vcxo has a dual control input: a binary input
and an integral input. The bang-bang part is only a few hundred Hz.

Unfortunately the vcxo control voltage is not available outside
the chip...

Thanks,
Stefan Simion

[...]
This delta(f) is more or less "flat" when the input frequency is well within
the pll lock range; it starts to increase towards the upper end of the lock
range; and decreases towards the lower end.

 

[Tim Wescott]

-- snip --
I don't know the fine details of the loop design (this is an ASIC)...
-- snip --
Unfortunately the vcxo control voltage is not available outside
the chip...

Oh, ouch. Time to severely beat the ASIC vendor about the head and
shoulders? Do you have any access to any part of the loop?

 

[Duncan Barclay]

There are some other (more direct) indications that the loop
may be unstable, namely large jitter being introduced under
some conditions. It does not always happen though, and the
measurements I am referring to are done when everything seems
to be working fine.

Is this temperature and/or supply dependent. It may be that the bias is
oscillating inside the IC. I've seem this happen, where the spur is
actually an injection locking of a bias circuit hooting. At some
frequencies the spur is reasonably clean but will move with frequency of
the main oscillator. At other frequencies the spur is very noisy.

One way of checking this may be vary the supply - if the spur changes
frequency it could well be oscillating bias.

I don't know the fine details of the loop design (this is an ASIC)
but from what I understand the intention was to have a single-pole
filter. In fact the vcxo has a dual control input: a binary input
and an integral input. The bang-bang part is only a few hundred Hz.

Unfortunately the vcxo control voltage is not available outside
the chip...

Thanks,
Stefan Simion

[...]
This delta(f) is more or less "flat" when the input frequency is well within
the pll lock range; it starts to increase towards the upper end of the lock
range; and decreases towards the lower end.

Now _that_ sounds like your loop is unstable, or at least severely
underdamped, with an oscillation frequency that tracks the differential
gain of the vxco over it's frequency range.

What kind of loop filter are you using? Is it active? How many
integrators? Pole/zero positions, etc.? It may behoove you to take a
look at the frequency command to the vxco and see what kind of content
it has.

 

[Stefan Simion]

Is this temperature and/or supply dependent
[...]
One way of checking this may be vary the supply - if the spur changes
frequency it could well be oscillating bias.

The spur frequency [offset] decreases when the VCC is lowered.
It is not linear; at nominal VCC the d(F)/d(VCC) is rather small.
At 70% VCC it moved from 61 kHz to 41 kHz.

But I guess other causes are also compatible with this observation?