PLL question

Hi,

I'm still a bit confused between lock range and capture range regarding
PLLs. I have the following definition:

* lock range - the range of frequencies that a PLL can maintain a lock
on the input signal
* capture range - the range of frequencies that a PLL can acquire lock
with an input signal... the capture range is never greater than the
lock range.

Am I right with the following?

- once a PLL locks to a certain frequency, the variation frequency from
which the input signal swings is in the lock range if the difference DC
component is still the same as to when the input signal is equal to the
locked frequency.

- say the lock range is up to 2kHz and the locked frequency is 5kHz,
then the PLL can still maintain a lock if the input signal swings 5kHz
+/- 2kHz.


??

Thanks!

 

I couldn't put it more clearly than that.

The only thing this sentence conveys is confusion.

Yes, if the lock range is +/- 2kHz about a *centre* frequency of 5KHz,
or to put it another way: if the lock range is from 3 KHz to 7KHz; but
not if the *locked* frequency was 5KHz and the range was 2 KHz from 5
to 7KHz.

 

I would add, "once lock has been achieved." The lock range may be
different for different rates of change of frequency, also. The
largest lock range would occur for very slowly changing frequency.

It might be a small part of the lock range. Some detector designs are
a lot better at following a slowly changing frequency around than they
are at capturing lock over a wide range.

I don't quite follow this. Why the introduction of DC?

I think I would state that lock range as from 3 to 7 kHz or 5 kHz
+-2kHz, but I would not call that a 2kHz lock range. I can't say that
this sort of description is unheard of, though.