# PLL Programming - Analog Devices

Discussion in 'Electronic Design' started by [email protected], Jul 6, 2005.

1. ### Guest

I'm currently working on a sweepable LO source for a receiver. I am
using a VCO in a PLL with an ADF4113 phase/frequency synthesizer chip
available from Analog Devices. I need to sweep the output frequency of
the VCO in a specific band. I was wondering if anyone has worked with
these chips (or similar) before. My issue is that I need to calculate
the best possible value for the "N" divisor given a frequency step size
of 1.3375MHz and I was wondering if anyone out there has developed an
algorithm for doing this.

Thanks for any help you may be able to provide me.

-Chris

2. ### Rene TschaggelarGuest

That shouldn't be such a problem. There is a
divisor dividing the reference down to the
channel distance aka comparator frequency and
then there is a divider dividing the output
frequency down to the channel distance.
The higher the divisors, the higher the phase noise.

Rene

3. ### ZenSafariGuest

Yes, calculating the divisor is no problem at all. My issue, however,
is that I need to select the optimal configuration for the divisor
given that:

N = (P*B) + A

I need to automate the calculation of P, B and A in software based on a
set of desired output frequencies to obtain the correct value for N. I
got something working yesterday that seems to do the trick, however.

4. ### Thomas MagmaGuest

I've done this. I wrote an app to generate all possible combinations between
two frequencies of interest. It puts the output values into a delimited text
file so you can import them into Excel and sort them based on frequency or
comparison frequency or what ever you want. It's written for a Pocket PC.

Thomas

5. ### John MilesGuest

If you have a choice, you'd normally want to minimize the N factor,
subject to the N >= P*P-1 constraint inherent in the dual-modulus
divider logic. The more multiplication the PLL chip has to do, the more
it will amplify the reference's noise (and its own inherent noise).
Your step size -- hence your comparison frequency, in a simple single-
loop PLL -- is 1.3375 MHz. That's a perfectly-reasonable comparison
frequency for these chips, so N should simply be your output frequency
divided by 1.3375 MHz.

P is the factor you'll actually have to choose. You didn't mention your
minimum output frequency, but let's say it's 1337.50 MHz. If N is 1000,
you can't use a prescaler value of 64, because 64*63 is 4032, much
larger than 1000. The next available P modulus is 32, which works (32*
31=992). Smaller P factors will work, too, as long as the prescaler's
output to the A/B counters is no higher than 200 MHz.

You *could* choose N to be some integral fraction of your step size, say
(output frequency / 1.3375 MHz) * 10. If your comparison frequency were
much higher than a few MHz, that might be worth considering... but I'd
say not in this case.

and take the results to the bank. It's good stuff.

-- jm

6. ### John MilesGuest

Sorry, I missed some parentheses: should be N >= P*(P-1).

-- jm