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PLL Phase Margin Measurement Technique

Discussion in 'Electronic Design' started by [email protected], Sep 25, 2006.

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  1. Guest

    Here it is:

    The "PLL Widget" they describe here:

    They claim this widget can be replaced with a simple resistor
    that is higher impedance than the output of the loop filter.

    But it seems to me that the loop is still closed in this case,
    unless the resistor is extremely high.

    It appears they keep the VCO in lock (closed loop),
    and add a perturbation between loop filter and VCO, and
    measure the amplitude and phase shift.

    All the literature i have seen refers to the Open loop bode
    response, typically G(s)H(s), in terms of calculating
    the phase margin.

    On the other hand, it seems like keeping the VCO in lock
    is the only practical way to do this.

  2. Tim Wescott

    Tim Wescott Guest

    Yes, they are keeping the VCO in lock, and operating the thing in closed
    loop. Yet they are still measuring the open-loop response of the PLL.
    This is done because they measure the output of the loop (Vx) and the
    input of the loop (Vy), _then they divide them_. The result, Vx/Vy, is
    the open-loop gain.

    This sort of measurement is common in control systems, and very useful.
    It is particularly useful when you have a system (like a PLL) which
    only conforms to a linear model when the loop is active.

    Here's an article to ponder on the general technique, which goes into
    more detail on the whys and wherefores: I hope
    it helps.


    Tim Wescott
    Wescott Design Services

    Posting from Google? See

    "Applied Control Theory for Embedded Systems" came out in April.
    See details at
  3. Mark

    Mark Guest

    See also

    they "invented" this technique..

    but I see now you have to give them your e-mail to get to the tech

  4. Genome

    Genome Guest

    Ridley also does one at shit loads of dollars a pop.......

    They don't work if your loop is not somewhere near stable in the first

    Of course Ridley also offers seminars where he explains how to analyse the
    loop in the first place, at shit loads of dollars a pop....... but you still
    need one at shit loads of dollars a pop which suggests something else.....
    Mind you, you also get 345 for free... normal price, shit loads of dollars a

    Still, these days there isn't much take up but there used to be a list of
    companies who enlisted their engineers on the seminar. Ooooh Dear, how

  5. Jim Thompson

    Jim Thompson Guest

    I use Middlebrook's method. See my website.

    ...Jim Thompson
  6. Guest

    Interesting stuff. All the phase-locked-loop stuff is
    directly from the control systems theory, but it's funny how
    you can say "good command following" to a PLL guy, and
    he still won't know what you mean!

    So really the "Open loop frequency/phase response"
    is really a misnomer, in the sense that you do NOT open the
    loop at all, but measure the closed loop at one point, with
    some sort of buffer (a resistor, or in your case, an adder) in
    between the injection point and the receive point.

    Are most of your control systems for mechanical things
    like elevators or robotic arms? Or more for like temperature
    or pressure or flow control systems?

    PLL design revolves around low phase noise, but I remember
    my control systems class talked about noise rejection with
    good command following, so i'm sure you worry about noisy
    signals too. For us, it's dBc/Hz @ xxx Hz Offset from the center
    carrier. Do control systems designers measure this with signal/noise
    ratios, or something like voltage % ripple on a command line?

    Thanks for you input, Tim.

  7. Guest

    That's some good stuff too, thanks.

  8. Tim Wescott

    Tim Wescott Guest

    Yes, but try saying "good lock acquisition time" and see what he says.
    Yes and no. It's what the response _would_ be if you could trust the
    plant in open loop. Some fortunate designers actually get to test their
    plants in open loop, most don't.
    * Precision mechanical loops that need to hold a target and reject
    * Fast mechanical loops that need to accelerate as fast as possible,
    decelerate as fast as possible, and come to a stop without bashing
    the end of mechanical travel.
    * Temperature loops (at 77 Kelvin, no less)
    * Video PLLs. This includes one that spans three microprocessors,
    three FPGAs, and two communications links -- yet still makes sense
    given the system it's embedded in.
    * Motor PLLs.
    * You name it.
    Usually the specification is in terms of the amount of acceptable
    deviation from a command, due both to poor command following and noise
    injection. Usually this specification is _not_ accompanied by any
    specified noise levels or command strengths, so some customer education
    and product-area research needs to be done.

    The control system part of controlling phase noise in a PLL is just good
    old disturbance rejection, but there's a lot of oscillator and phase
    detector choices in there that aren't directly involved in control
    theory (but whose desirable characteristics certainly are informed by
    control theory).


    Tim Wescott
    Wescott Design Services

    Posting from Google? See

    "Applied Control Theory for Embedded Systems" came out in April.
    See details at
  9. Mark

    Mark Guest

    No it's not a are measureing or determining the open loop
    gain and phase of the loop but you are making the measurement while the
    loop is closed. The true closed loop response of a PLL loock like a
    low pass filter. These techniques give you the open loop response.

    If you were to really open the loop, it would rail out and you could
    not make any measurements. I think the widget thing actually does open
    the loop for all frequencies except the very low frequencies.

    The Venable method keeps the loop fully closed but is still measuring
    the open loop response...that's why it is so slick..

  10. Guest

    Point well taken.

    If we look at this:

    By definition, the closed loop response is Theta out/ Theta ref,
    which is obviously not the same as injecting and receiving a signal
    before and after a buffer at point 3.

    The widget is a sort of low pass filter, but the loop is still
    fully closed.

    But yes, the VCO would be free-running if the loop was truly
    open, and the correction voltage from the phase frequency detector
    would be all over the place, instead of the low frequency baseband
    correction frequency that we would have with two phase-locked sources.

  11. Guest

    That would be well understood. Aka, "fast acquisition time",
    "fast settling time."

    Yeah, too bad we can't trust our VCO to stay in one
    place for very long (locked to the reference), otherwise we
    could REALLY open the loop and take a measurement.

    Interesting. Are you using root locus techniques for
    positioning poles and zeros in the s-plane?

    I never got too deep into that stuff, but if i'm not
    mistaken, the unity gain frequency of the open loop @
    -180 degrees will be a pole in the right hand plane, right?

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