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PLL locking problem

Discussion in 'Electronic Design' started by cici, Dec 1, 2003.

  1. cici

    cici Guest

    My PLL can not lock. I am using an XOR as the PD, cross coupled VCO.
    The control voltage is in the tuning voltage range of VCO. However, it
    is an oscillation the same frequency of the output of the PD. When the
    PLL is locked, the voltage should be a straight line. What can be the
    problem? Thanks!
     
  2. markp

    markp Guest

    The output from an xor phase detector will be a 50% square wave when in
    lock, i.e. the RC network will be charged and discharged at the same rate
    maintaining a fixed frequency. It sounds like it's working fine. Maybe
    you're getting confused with an edge detecting PD?

    Mark.
     
  3. Baphomet

    Baphomet Guest

    Check your phase. The control voltage may be driving your VCO away from
    lock.
     
  4. John Larkin

    John Larkin Guest

    Sounds maybe like a loop stability problem. I've built PLLs that were
    so unstable that they did all they could to run away from locking. If
    you don't know this stuff already, get a good book on PLL dynamics.

    Are you using a lowpass filter after the PD? Got any more details?

    John
     
  5. John Larkin

    John Larkin Guest

    I think an XOR pd will just lock on the opposite edge if the loop
    phase is reversed.

    John
     
  6. Baphomet

    Baphomet Guest

    I can't really remember because it was sooo long ago, but I ran into a
    similar problem and it was driving me nuts. I flipped the phase of something
    (although I can't rember what or how) and it worked just fine after that.
     
  7. Jim Thompson

    Jim Thompson Guest

    John, You *are* correct (except it's not *edge*, but on the opposite
    90° phase). I think the OP's problem is *lack* of an appropriate
    filter.

    ...Jim Thompson
     
  8. markp

    markp Guest

    Indeed, it sounds like there's no filter at all if the control voltage is
    oscillating at the same frequency as the PD.

    Mark.
     
  9. Jim Thompson

    Jim Thompson Guest

    Should be at *twice* frequency... maybe he has a mis-wire.

    ...Jim Thompson
     
  10. markp

    markp Guest

    I think the OP says it's the same frequency as the output of the PD, which
    as you say should be twice the frequency of the VCO in lock.

    Mark.
     
  11. Luhan Monat

    Luhan Monat Guest

    Bingo!
     
  12. maxfoo

    maxfoo Guest

    probably talkin' bout differential type phase detector, yeah i get the polarity
    reversed too.


    Remove "HeadFromButt", before replying by email.
     
  13. cici

    cici Guest

    Yes, I am using a RC low pass filter, followed by a source follower.
     
  14. John Larkin

    John Larkin Guest

    Try adding a small R in series with the C... that will damp an
    otherwise very ringy loop dynamic.

    John
     
  15. Genome

    Genome Guest

    Hmmm.

    Excuse me but........ didn't you suggest that DM, or some other, was in the
    realms of suck it and see coz you thought you were so ded clev at doing the
    job proper?

    And then you suggest adding a small R in series with the C to deal with a
    ringy loop dynamic.

    That is a big fucking schnort......

    No offence meant but....... c'mon.

    DNA
     
  16. John Larkin

    John Larkin Guest

    Heavens, you're surely not...gasp...sputter...comparing....

    Well, geez, I can't deliver a 2-semister course in control theory in a
    newsgroup. I did suggest, somewheres north of here, that the OP get a
    good book on PLLs. The resistor is the typical bottom line here, so
    let the guy give it a try; the notion *is* theoretically sound, ain't
    it? Maybe?

    John
     
  17. Genome

    Genome Guest

    Could be three or four easy steps, or perhaps one or two..... mind you it'll
    tax my small one.

    Step 1)

    Wot's the gain of the EXOR gate?

    NAND
     
  18. John Larkin

    John Larkin Guest

    They tax your small one? I guess there's a VAT on everything over
    there.

    Step 2)

    Wot's the transfer function of the VCO?

    (You do #3; it gets harder from here on.)

    John
     
  19. Genome

    Genome Guest

    So.... don't be an old fart. If you give me 1 and 2 then number 3 should
    drop out of my bum.

    Caveat is you tell me and the rest of the planet what 1 and 2 is.

    DNA
     
  20. Tom

    Tom Guest

    Soumds like classical instability problem. Measure the frequency of
    oscillation and you can get back to the transfer function - it will be
    something like

    K/s*(1/(1+sT)

    where K is your unknown gain. To find K you will need to draw a Bode plot
    or do a calculation which takes the magnitude of the above and sets it to
    unity using the measured oscillating frequency - then work back to K.
    Once you have K you can do a proper design.
    I expect the phase margin is pretty much non-existant. What you really
    need is a lag-lead compensator. A series resistor (sombody mentioned that)
    and a parallel resistor across the capacitor to give a steep roll-off at
    high frequencies (for noise attenuation).You could try fiddling but these
    things are best calculated otehrwise it is a shot in the dark. Trouble is
    nobody does control courses anymore - they all want to do digital!

    Tom
     
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