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PLL input filter vs. loop filter

Discussion in 'Electronic Design' started by Tom Becker, Apr 9, 2006.

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  1. Tom Becker

    Tom Becker Guest

    Folks, I've been working with a 4046-based shaft rotation tracking PLL
    circuit. The source is a weak, noisy and pretty sloppy
    inductively-generated shaft speed signal. I want to regenerate and
    track it's principal signal of 252Hz, but that is punctuated with
    occasional large and sometimes periodic low-frequency resonances and
    gear noise.

    The physical device is subjected to random accelerations from any
    direction so while tracking it must remain responsive to pretty rapid
    input phase and frequency changes - yet be able to flywheel though the
    missing cycles caused by the resonances.

    That seemed a challenge, but I have found reasonable success with simple
    passive filters for some input conditioning, and for the loop filter.
    While experimenting with active filters, though, I've found that any
    low-pass on the input reduces responsiveness, thus tracking. As I write
    this, I think I see that's due to any integrator eating time.

    That suggests that whatever low-pass filtering I need should be done in
    the PLL loop, not ahead of it. That leaves me with the low-frequency
    resonance effect inside the loop, though, and that can ding the VCO
    pretty well - producing a cycle-slip or breaking lock.

    I'm tempted to try a twin-T notch or a high-pass to remove the low-F
    stuff ahead of the loop, but I know I'm still playing with time. In
    general - intending to optimize for tracking - should I try to clean up
    the signal ahead of the PLL or be more selective in the loop filter?

    Or am I off track? TIA.

  2. John  Larkin

    John Larkin Guest

    What's the actual signal frequency range? 252 Hz +- what?

    If it's narrow, a bandpass filter is appropriate. Its bandwidth should
    be narrow to kill noise but wide enough to allow it to track changes
    in the signal frequency. It's possible that all you need is a good
    bpf, no pll at all.

    A 4046 requires a logic-level input to any of its phase detectors, so
    I assume you have a comparator in the front-end somewhere. If so, that
    will make trouble at low s/n. A linear phase detector (a multiplier or
    a synchronous rectifier) is better at pulling a weak signal out of

  3. Tom Becker

    Tom Becker Guest

    ... 252 Hz +- what?

    I'm expecting +/20% instantaneous error.
    Maybe a tracking BPF, yes.
    I'm using PC1 of the 74HC4046, the XOR comparator. I had no fortune
    with either of the edge detected phase comparators. Although I am using
    an opamp as a comparator at the moment, it has offered no advantage over
    the biased inputs of the modern IC, which permit 20mVPP AC-coupled inputs.

    A tracking BPF. Hmmm. Thanks.

  4. Tim Wescott

    Tim Wescott Guest

    Even the XOR still needs a logic input, which tends to magnify noise
    when the SNR is low. John's suggestion of replacing the XOR with a
    multiplier is not to be ignored, but a tracking BPF may be the better
    thing to try first.


    Tim Wescott
    Wescott Design Services

    Posting from Google? See
  5. Joerg

    Joerg Guest

    Hello Tom,

    The frequency is kind of low for this but it might be worth checking it
    out: The old technique of Q-multipliers. Basically these are resonant
    circuits where the connected stage is adjusted in feedback so that it
    just doesn't oscillate. The closeness to the point of oscillation
    determines the bandwidth, the closer the narrower.

    This doesn't need to be LC, maybe a gyrator filter? Anyway, it'll take
    some serious studying and simulating to make sure it is stable and has
    the behavior you are after.

    If by +/-20% you mean the deviation in rpm you'd have to start it pretty
    much wide open and then have it narrow down. It almost sounds like a job
    for a uC or low-end DSP.

    A PLL could work as well. But I'd consider something better than the 4046.

    Regards, Joerg
  6. Ken Smith

    Ken Smith Guest

    Check out the self biasing circuit on pin 14. You only need provide a
    coupling capacitor and the 4046 will work with a sine wave input.
  7. Ken Smith

    Ken Smith Guest


    If you are making in multiplying PLL and have a lowpass before the
    comparitor, you can feed a small sawtooth, made from the VCO, into the
    comparitor to cause it to PWM. This allows you to multiply moderately
    well without a true multiplier.
  8. John  Larkin

    John Larkin Guest

    But it's still effectively a comparator, with its consequences, namely
    "capture effect" where big signals blow small signals away.

  9. Ben Jackson

    Ben Jackson Guest

    You can't track "instantaneous" error. In the PLL, the bandwidth of
    the low-pass filter on the output of the phase detector determines
    the agility of the PLL. Tracking "instantaneous" error would be
    equivalent to not having a PLL at all (in your 1:1 case). In your
    first post you said:
    Once you quantify "pretty rapid", then you know the bandwidth of the
    loop filter when you have an input signal. Then "flywheeling" would
    be equivalent to switching in a low-bandwidth loop filter when the
    input signal is invalid. The problem, then, is detecting when it's

    What about this:

    signal --> phase detector --> high-bw lowpass just to convert
    phase detector pulses to voltage --> clamp to a voltage equivalent
    to 252 +/-20% at the VCO --> lowpass filter to "pretty rapid"
    rate --> vco --> back to phase detector

    So now if you miss a pulse, the clamp after the first filter stage will
    clamp that to 252-20% and the whole PLL will start slewing toward that
    rate at the "pretty rapid" rate. If you continue to miss input signals,
    eventually "no input" will become 252-20% steady state.

    If you expect to lose signal long enough that the "pretty rapid" rate
    will see an unacceptable change, you could take the output of the first
    filter stage, detect V < 252-20% with a comparator and use that to
    dramatically reduce the bandwidth of the second filter stage (or switch
    in a circuit that can quickly sample and hold the current VCO input

    For a super slow speed like this, the idea of using a micro that someone
    else had is probably even better...

    The problem with a filter in front of the PLL is that you can't "remove"
    missing pulses. A low-pass filter would work fine if you were seeing
    extra pulses...
  10. Joerg

    Joerg Guest

    Hello Ben,
    True. 250Hz is easy to do. The MSP430F2013 contains a 16bit engine and a
    16bit SAR converter. Seems almost ideal for this app. When there are too
    many unknowns in the signal characteristic a uC allows easy adaptation
    of algorithms, including a lot of stuff that simply cannot be done in
    the analog domain with any reasonable effort. That was hard to say for
    me as an analog guy but 'tis how it is.

    If the F2013 aint't enough there is the F4xx family. These come with
    more RAM and hardware multipliers. Like the Camaro of the MSP430 series.

    With a uC you probably could.

    Regards, Joerg
  11. Tom Becker

    Tom Becker Guest

    ... feed a small sawtooth, made from the VCO, into the comparitor to
    cause it to [] multiply moderately well without a true multiplier...

    Very interesting, if I understand. Can you find a link to an example?

  12. Tom Becker

    Tom Becker Guest

    You can't track "instantaneous" error.

    Yes; my poor descriptor should have been "maximum brief" error, probably.
    No, but I believe the "missing pulse" - actually a missing
    zero-crossing, I think - is just an artifact of the summation of several
    signals. Envision 252Hz riding on an 18Hz narrow Gaussian pulse and
    you're close. I often see 13 pretty clean cycles of 252Hz, then a flat,
    then 13..., instead of 252/18=14.

    Can't I just notch the 18Hz? Can it be done in the loop filter?

  13. John  Larkin

    John Larkin Guest

    How about using a switched-capacitor bandpass filter? Design one
    filter section to give a 90 deg phase shift at filter cf (that stage
    would actually be a peaked lowpass, technically). Hang a phase
    detector across that stage's input and output, lowpass filter, and
    servo a v/f as the clock of the filter. That could be a tracking bpf
    with just a few ic's.

  14. Jim Thompson

    Jim Thompson Guest

    The way to do it: NARROW PLL restores the carrier, then multiply
    noisy signal with restored carrier. It's called correlation ;-)

    ...Jim Thompson
  15. Tom Becker

    Tom Becker Guest

    How about using a switched-capacitor bandpass filter?

    Did it. At one point I had a /8 in the loop; I clocked an eight-cap
    Tayloe filter with the VCO. Spectacular selectivity and fun to
    implement; it's like a _visual_ filter on a scope.

    I had a lot of trouble with the loop, though; essentially nothing got
    through the Tayloe if it was unlocked - so it was hard to lock and hard
    to keep locked. It just wasn't very stable trying to follow a
    mechanical clock source; too sharp, probably.

    The tracking BPF started me thinking about it again, though. I've
    learned much since then so maybe I'll visit this again.

  16. John  Larkin

    John Larkin Guest

    Is that one of those Resistor/rotary switch/buncha caps things? Those
    are so cool. But I was thinking about a commercial IC switch-cap
    bandpass, an MF10 sort of thing, or one of the more modern versions.

    Maybe most of the selectivity could be downstream of where the phase
    detection is done. That almost defies logic, a narrowband tracking
    filter with fast, wideband tracking ability. That wouldn't be real bad
    as long as the noise was fairly incoherent.

    Next step, FFT?

  17. Tom Becker

    Tom Becker Guest

    Next step, FFT?

    I guess that's not out of the question. At Joerg's suggestion I took a
    look at the MSP430F2013. Unbelievable for $1.50. I'm hesitant to pick
    up another platform - I'm an old 8008 guy who's settled on AVRs for now
    - but fast 16-bit mixed-signal processing is very inviting. [It's got a
    PGA on the ADC input, too. I dream of a processor that offers an
    on-the-fly programmable analog signal processing section; this is
    getting close.]

    Suppose a sufficiently fast and resolute FFT was available, though.
    What subsequent function counts cycles in a narrow range of FFT bins?
    How do you get from an FFT to a regenerated clock?

  18. Ban

    Ban Guest

    finally a good answer by someone who knows. Take a venerable NE567 or
    XR215A, put a bit of amplification and maybe 200Hz highpass in front of it,
    so the signal is in the 20 to 100mV rms range. Set the BW to 1% and after
    200cycles the output goes low and signalles your PLL locked. You can tap
    into the squarewave output to get a stable reference without missing pulses.
  19. Ken Smith

    Ken Smith Guest

    Yes I agree. The input does act as a comparitor.
  20. Ken Smith

    Ken Smith Guest

    No and it I told you where I saw it used ....
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