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Please help on inverters

daGenie

Jan 23, 2012
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Please can somebody answer these 2 questions?

How do I determine the output frequency of a 555 timer used as an oscillator in a power inverter?

Why does the output waveform of the 555 timer have to have a duty cycle close to 100%?

Any answer would be highly appreciated.
 

(*steve*)

¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd
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Jan 21, 2010
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1) You can either measure it or calculate it.

2) In general it doesn't. Maybe it does in your circuit, but you haven't told us what it is.
 

daGenie

Jan 23, 2012
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1) You can either measure it or calculate it.

2) In general it doesn't. Maybe it does in your circuit, but you haven't told us what it is.

Ok, according to all the circuit diagrams i've seen that use a 555 timer as their oscillator, the 555 timer is set up in monostable mode i.e. there is no resistor between 6 and 7. Because of this, the capacitor must discharge immediately, making it's duty cycle to be very high. I've seen two circuits like this and i really don't understand why it's like this. Is there anyway it could be constructed with 50% duty cycle?

And concerning the calculation, do i use T = 1.1RC, since the 555 timer is connected in monostable mode? Or is there some kind of special way.
 

daGenie

Jan 23, 2012
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sorry, i made a mistake. The 555 timer is still in astable mode, but there is no R2 resistor...this would make the duty cycle large. Canan you explain why this duty cycle is made large in some power inverter circuits?
 

duke37

Jan 9, 2011
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For a push/pull invertor you need to push equally to pull. You can do this with an oscillator (555) followed by a divide by two.
The CMOS 4047 can do this in one chip.
 

daGenie

Jan 23, 2012
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For a push/pull invertor you need to push equally to pull. You can do this with an oscillator (555) followed by a divide by two.
The CMOS 4047 can do this in one chip.

can you explain how cmos 4047 works please
 

(*steve*)

¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd
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Jan 21, 2010
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Google "4047", click on the first link, read it, then come back to us if you have any questions.

And show us the circuit diagram of whatever it is that you're building. The 4047 may be totally inappropriate.

We can't operate in a vacuum!
 

Rleo6965

Jan 22, 2012
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It looks like a astable freq was 120 hz and divide by 2 by 4047 flip flop and RC on base of Q1 and Q2 was a sine wave forming circuit. So that secondary output of transformer would be 220V , 60 hz, simulated sinewave.
3V ac circuit w/ bridge rectifier and CA3130 will be the over voltage feedback control circuit by enabling/ disabling ic 4001 60hz square wave pulse. I guess.:eek:
 
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(*steve*)

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It looks to me that the voltage across the timing capacitor is used as a ramp which is compared to the secondary voltage in order to regulate the output.
 

duke37

Jan 9, 2011
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The link you gave seems to be infected with advertisements and is difficult to get out of.
After a time I managed to get some of the diagram and it looks like an old design. It uses npn transitors to switch the current. These need a large base drive and waste perhaps a volt. Much of the circuit is to provide the large base drive.

I would go for fet switches which have a very low resistance when turned on and need very little gate drive at low frequencies.

A 4047, two IRF540 fets, one capacitor and three resistors would do the job on the primary.
Please tell us the frequency, transformer type and power demand.
 

duke37

Jan 9, 2011
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Sorry, I missed the second page so what I said is somewhat irrelevent.
 

Rleo6965

Jan 22, 2012
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Ok, according to all the circuit diagrams i've seen that use a 555 timer as their oscillator, the 555 timer is set up in monostable mode i.e. there is no resistor between 6 and 7. Because of this, the capacitor must discharge immediately, making it's duty cycle to be very high. I've seen two circuits like this and i really don't understand why it's like this. Is there anyway it could be constructed with 50% duty cycle?

simulatedsinewaveinverter.jpg



To answer question of daGenie.
Basing in your diagram. There's no connection on pin 7 or discharge pin of 555 ic. It uses pin 3 output as discharge pin. So pin 3 was both serve as output and discharge pin for the 555. With this configuration of 555 it will not have a 50% duty cycle.

To have a fifty-fifty duty cycle. 555 must be 120hz to its output and fed to 4047 flip flop. In this way , each cycle of 555 output will toggle the output of flip flop. That is, it will take 2 cycle of 555 to have 1 complete cyle to output of 4047 flip flop This therefore result a real 60 hz 50-50 duty cycle. Just like the ac sine wave duty cycle.
 
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duke37

Jan 9, 2011
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I do not uderstand the circuit, it looks as if the width of the pulses are adjusted depending on the peak voltage of the pulses but I do not see any voltage reference. Depending on the application, this may not be advisable or required.

All the transistors could be replaced by two fets with lower cost and a better efficiency.
 
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