Connect with us

Pipeline ADC question

Discussion in 'Electronic Design' started by Michael, Jun 9, 2004.

Scroll to continue with content
  1. Michael

    Michael Guest

    How many clock pulses does a pipeline ADC need to settle?
    In other words: if I have clock coming in bursts, what is the minimum
    burst length I need to get the right reading.
    I need 5.5 clocks after the sample of interest to get the data. How
    many clocks do I need before?
    One of the parts in question is TI ADS5102.
    Thank you very much.
    P.S.: I have not been able to get the answer from the manufacturer(s)
    Trying it out seems to be a pain, but I am considering it...
  2. John Larkin

    John Larkin Guest

    They vary, in the 3-7 clock range. See the datasheet.

    But most of these ADCs really want to see a continuous clock, and may
    not work well in a burst mode. Leave the clock on all the time if you

  3. It varies, my experiance with TI dsp's is 2-3 clocks with a good low impediance buffer feeding the ADC input.

Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day