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Pipeline ADC Digital Correction Algorithm

V

Vincent

Jan 1, 1970
0
Dear all:



I'm designing a 12bit piepline adc (very conventional one). it's based
on 1.5bit/stage + 3bit (last stage). In some papers and products
specs, there are more than enough stages over all, say: 12 1.5bit
stages and one 3bit stages. I'm just wondering what algorithm in this
case, after RSD digital correction, there will be 15bit resolution and
discard last 3 stages?! What's benefit behind this "luxurious"
correction?

Appreciate your help.



Vincent
 
F

Fred Bloggs

Jan 1, 1970
0
Vincent said:
Dear all:



I'm designing a 12bit piepline adc (very conventional one). it's based
on 1.5bit/stage + 3bit (last stage). In some papers and products
specs, there are more than enough stages over all, say: 12 1.5bit
stages and one 3bit stages. I'm just wondering what algorithm in this
case, after RSD digital correction, there will be 15bit resolution and
discard last 3 stages?! What's benefit behind this "luxurious"
correction?

Appreciate your help.

It almost certainly would have to do with overcoming the differential
nonlinearity of the conversion- this is by far the greatest contributor
to resolution error.
 
J

John Larkin

Jan 1, 1970
0
Dear all:



I'm designing a 12bit piepline adc (very conventional one). it's based
on 1.5bit/stage + 3bit (last stage). In some papers and products
specs, there are more than enough stages over all, say: 12 1.5bit
stages and one 3bit stages. I'm just wondering what algorithm in this
case, after RSD digital correction, there will be 15bit resolution and
discard last 3 stages?! What's benefit behind this "luxurious"
correction?

Appreciate your help.



Vincent

In addition to the DNL improvement Fred mentioned, people tend to
design one chip they can sell as various part numbers with different
resolutions. Sometimes they just don't bond-out the unused bits.

John
 
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