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Phase Locked Loops for 30-50MHz

Discussion in 'Electronic Design' started by [email protected], Jul 13, 2006.

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  1. Guest

    Hi everybody:

    I need to take an input clock signal and reproduce a phase locked,
    identical frequency output signal. The problem is that the input
    signal is 30 - 50 MHz. Now the other problem: the PLL must acheive
    lock in under 30 - 35us. Do y'all have any recommendations for PLL ICs
    that will work with these specifications?

    TI has the most promising ICs, but the lock times might be to long. I
    have contacted TI to see if they can give me a better estimate using my
    freq. ranges, but thought I would ask around for other IC
    recommendations in the meantime.

    The two TI ICs are:
    1.) http://focus.ti.com/lit/ds/symlink/sn65lvds150.pdf
    2.) http://focus.ti.com/lit/ds/symlink/tlc2932.pdf

    Another question that I had was this: some of the Philips PLL don't
    have an upper freq. limit on their VCO, how is this possible?
    Specifically HEF4046B.

    Thanks in advance,
    Austin McElroy
     
  2. Guest

    Have you considered a non "chip" design? You say you want to lock
    on a incoming 30-50 mhz. I dont have the schematics of this with me
    today but I could scan them in tomarrow. I have a book at home with a
    simple circuit used to lock a vco at harmonics of 1 mhz, but it would
    not be hard to hack it to go 1:1 with a input frequency. I have built
    the circuit and it works well. I'm assuming you want to demodulate
    something with the VCO control voltage?

    simple first order loop:
    incoming signal is buffered then goes into one side of a mini-circuits
    phase detector. Other side is fed by a POS-70 VCO also from
    minicircuits, via a isolation amp, say a MAR-4. The phase detector
    output goes to a fast opamp that adds gain and offset, output of opamp
    goes to a three or four component passive filter then to VCO control
    voltage. No dividers, no programming, no math. Has a tendancy to be
    able to lock up on subharmonics and harmonics though.

    I'm not a expert in PLLs by any means, but from your description this
    sounds like it would do what you want.

    Steve Roberts
     
  3. Guest

    Thanks you for the response:

    I have considered a non-IC design, but I am worried that a hand built
    circuit would have even worse lock times than a proffesionally designed
    circuit. I am pretty new to PLL and besides the lock issue, those ICs
    look like they fit the bill, depending if I wanted to go analog or
    digital.

    I will not be demodulating anything, i just need to get a 1:1 signal
    out.

    Thanks,
    Austin McElroy
     
  4. Mark

    Mark Guest

    OK obvious question...if you already have the signal ....why not just
    use the signal itself .....why do you need a PLL?
     
  5. Rich Grise

    Rich Grise Guest

    That's odd. On page 8 of the data sheet I'm looking at:
    http://www.semiconductors.philips.com/acrobat_download/datasheets/HEF4046B_CNV_3.pdf
    it says, "Maximum operating frequency", and it has three values for Vdd of
    5, 10, and 15V.

    Good Luck!
    Rich
     
  6. Guest

    Again, thanks for the replys.

    To Mark:

    The signal dies off after a few micro seconds, and we would like to
    keep it going after it dies down. This is why I need the fast lock
    time and the 1:1 output.

    To Rich:

    The 3 Voltages are just for 3 different power states, no big deal.
    There is no upper freq. listed on the spec sheet. Surely I can't use
    the VCO to ouput 30 GHz. Why is an upper freq for the 3 different
    power modes not listed?

    Thanks,
    Austin McElroy
     
  7. Ken Smith

    Ken Smith Guest


    I think your frequency is too high for this to work but I'll throw the
    idea in here because we may be able to adapt it:

    Make your VCO run at many times the input frequency. Add some logic to
    the reset input of the feedback divider of the PLL. This logic holds the
    feedback divider reset until the signal arrives. At the first edge of the
    signal, the counter is allowed to start running in step with the signal.

    The filter of the PLL contains some sort of multiplier function like a
    CA3080 or a LT1228 so that its bandwidth can initially be made very wide
    and then smoothly narrowed.

    By starting the counter in phase, we can be certain that the error signal
    has the right phase at the start. The varying bandwidth means that this
    correct error signal will quickly bring us to almost the right frequency.

    The smoothly narrowing bandwidth means that there is less of a tendancy to
    trap errors due to noise. For simple cases, the classic RC based
    exp(t/RC) shape is a good one to use. Your noise enviroment, will
    determine the ideal shape.
     
  8. Rich Grise

    Rich Grise Guest

    Well, if you can't figure out what this means:

    Parameter VDD Symbol Min. Typ. Max Notes
    Maximum operating 5 0,5 1,0 MHz VCOIN at VDD;
    frequency 10 fmax 1,0 2,0 MHz R1 = 10 k; R2 = infinity;
    15 1,3 2,7 MHz C1 = 50 pF

    Then you're probably in the wrong line of work.

    And yes, since the max. freq. at 15V Vdd is typically 2.7 MHz, then no,
    you can't use it at 30 MHz.

    Good Luck!
    Rich
     
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