# phase lock loop(PLL) doubt

Discussion in 'Electronic Basics' started by biras, Jul 12, 2005.

1. ### birasGuest

hi
i saw one PLL(4046) example. the example say ,PLL will work from
50hz to 80hz input frquncy (phase comparator input frequency),

1)i want to know if input frequency is lessthan or greaterthan this
range what will happen,

2)how PLL is identifying this range

2. ### PeteSGuest

For the fast tour ....

Without knowing the details of the reference design you saw, the two
frequency ranges (at the input) of interest of any PLL are:

Lock range (Acquisition range)
Hold-in range

[Other frequencies of interest in a PLL include the phase rate (the
rate at which the input frequency can change) the PLL can follow and
loop frequency (the filter characteristics of the loop filter in the
frequency domain) - these two are closely related in terms of PLL
performance].

At the output we care about the ouput VCO range (which may be directly
fed back or may be sent through dividers as is done in frequency
synthesis).

Both *input* ranges are a function of the VCO (the VCO Fout/Vin
function determines the output frequency range of the VCO), the phase
detector and the loop filter (and divders if present), but typically
Hold-in is wider than lock, although not always.

If the frequency is higher or lower than the acquisiton range (assuming
it is unlocked),
PLLs will do one of a number of things, depending on whether there is a
signal present or not, and whether it is within the lock/hold-in range
of the input

a. Sweep across their frequency range (Sawtooth applied to VCO
V[control] as the phase detector gives a varying output (common if
F[in] is outside the lock range of the PLL, but depends on the
characteristics of the phase detector)

b. Sit at a single frequency (except for jitter) - common for many PLLs
in the absence of a signal.

As to 'How does it know the signal is within that range' - the range of
frequencies a PLL can cover is determined by the overall
characteristics as noted above.

Cheers

PeteS

3. ### Andrew HolmeGuest

It depends which phase detector you're using. Using PC2, the loop will
sit at fmin or fmax, with 0V or Vdd on the VCO control line, if the
input frequency lies outside the VCO tuning range. The behaviour of
PC1 is more complex; it can lock on harmonics.

PC2 can capture and hold lock over the full VCO tuning range.
PC1 has a narrower capture range.

4. ### birasGuest

hi
i have some doubt please clear me

1) i want to operate the pll in 12.5 kz frequency then,what would be my
VCO centre frequency? will it be 12.5 khz or some thing else.

2)In phase comparator 2 fc=fL , will the PLL work when the frequency
differnce between the singnal IN(pin 14) and comparator IN(pin no 3) is
below the fL range?(pll no 4046)

3) what are thnigs i want to take care for designing the loop
filter?,(if u know any design formula plz send to me)

birasanna