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Phase lock loop 4046 ( band width)

Discussion in 'Electronic Basics' started by biras, Aug 15, 2005.

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  1. biras

    biras Guest

    hi
    1)how can i find loop filter (lead_ lag passive) bandwidth?. And the
    phase comparator output frequency with this range?

    this the first time i doing the pll. so plz kindly help he
     
  2. Andrew Holme

    Andrew Holme Guest

    You can find the -3dB bandwidth of your filter by drawing a Bode plot
    of its transfer function. However, I suspect what you really want is
    the bandwidth of the loop. This depends on VCO, divider and phase
    detector gain as well.

    Personally, I do Bode plots of open and closed loop responses using
    SCILAB.

    I don't know what you mean by "phase comparator output frequency with
    this range"
     
  3. biras

    biras Guest

    Thanks for your replay i will try it. my second question is not
    pointing clearly.i will send later

    one more question
    1) if PLL is not locked,Then vco output frequency is same as centre
    frequency or not?
    Thanking you

    biras.R
     
  4. Andrew Holme

    Andrew Holme Guest

    It depends on whether you have an input signal or not, and on which
    phase detector you're using. Without an input, the XOR gate takes it
    to the centre, but the edge-sensitive PFD pulls it down to fmin.
     
  5. biras

    biras Guest

    hello

    Thanks for your replay

    one more question(pll 4046)
    1) my sign in (pin 14) frequency is 50HZ, and i need vco output
    frequency is 204.8KHZ (50* 4096 times).i using pc2
    comparator,passive filter and i added divide counter in feedback
    path(4096)

    i want allow the sign in frequency change 35 hz to 65hz.so i choose
    Fmin is 143.3KHZ(35*4096),Fmax is 266.4KHz(65*4096),center frequency
    204.8KHZ

    i choose R1,R2,C1according to this formulas


    Fmin=1/(R2(C1+32PF))

    Fmax=(1/R1(c1+32PF)))+Fmin
    c1=1000pf
    Filter

    R4 C2 =( 6N / fmax) – (N / 2Л Δf)
    (R3+3000) c2 =((1000N Δf/fmax2) – r4 c2)
    c2= 4E-06
    Definitions: N = Total division ratio in feedback loop
    Δf= fmax – fmin


    i did the design like this,but i not geting what i expect

    if i remove the sig in(pin 14) then vco output frequency is 139Khz
    if i give the vcoin as 5v then vco out is 139 khz
    Then i connect close loop,and if any phase difference there between
    the signal my vcoin is varying .but my Vco output is 139khz


    i sure my connection is perfect
    i can't find the mistake. so plz help me
     
  6. There is no point worrying about closed loop operation till you can
    get about Fout=143 kHz with a VCOin=0 volts and Fout=266kHz with
    VCOin=Vcc. If your RC values do not produce these frequencies, either
    your formulas are wrong, or your components are not what you think
    they are, or your chip is defective.
     
  7. biras

    biras Guest

    hi
    i need frequency multiplier application notes using Phase lock
    loop(pll 4046) circuit.
    if anybody know plz forward me.
     
  8. PeteS

    PeteS Guest

  9. biras

    biras Guest

    hi
    one basic fundemental questions(pLL 4046 ,pc2)
    !) if my input signal is varying continously(with in the level),
    corresponding VCOIN voltage also vary,than what about VCO output
    frequency?,whether it vary and settled any one frequency or the output
    frequency continously vary according to vocin?
     
  10. PeteS

    PeteS Guest

    Provided the input signal variation rate is within the loop bandwidth
    [at least to a first approximation], the the VCO output will vary
    proportionally. That is, if F(in) has a rate +/-f, then the VCO will
    vary it's output frequency at a rate f.

    If the input variation rate is beyond the loop bandwidth, then the loop
    will probably break lock. What happens then depends on the
    characteristics of the loop.

    Cheers

    PeteS
     
  11. Andrew Holme

    Andrew Holme Guest

    Varying how? In amplitude, phase or frequency? What does "within the
    level" mean? Is it not a square wave? Do you have drop-outs?
    If VCOIN is not a steady DC level, then you will have phase/frequency
    modulation on the VCO output; so yes, the output frequency continously
    varies with VCOIN.
     
  12. biras

    biras Guest

    Hi
    thank u for reply
    (pll 4046 , pc2,passive filter )
    i was designed pll in 12.8 KHZ as center frequency(f0= 2.5),i choose
    The VCO Resistance, capacitor according to formula,The value is R1
    100kO R2 25kO c.01micro F,

    Then i connect VcoIN to ground then my VCO output is 11.7Khz
    Next i connect Vcoin to 5V Then o/p is 12.92Khz

    Then i connect to closed loop.
    Now i/p frequency Sig In (pin 14) 50 hz,
    VCO o/p is 12.5Khz,
    Vco In VARY 4.1volts to 4.3volts
    feed back Input (pin 3) IS 47.8 hz , Because In feed back path i
    added divide by 256 counter ,

    And The pulse output goes zero to 5v,like that,i think it MUST travel
    from 5 v to zero volt
    __________ 5v __________
    l l l l
    l l l l
    l l l l
    _____l l__________________________l l 0V



    This is overview of my circuit,

    i want to change the MY 2fl at least 4khz and i expect my f0 at 2
    volts.

    And i changed the R1,C1 value . But i not getting what i expect,
    so plz give some key to open my lock.
     
  13. biras

    biras Guest

    Hi
    thank u for reply
    (pll 4046 , pc2,passive filter )
    i was designed pll in 12.8 KHZ as center frequency(f0= 2.5),i choose
    The VCO Resistance, capacitor according to formula,The value is R1
    100kO R2 25kO c.01micro F,

    Then i connect VcoIN to ground then my VCO output is 11.7Khz
    Next i connect Vcoin to 5V Then o/p is 12.92Khz

    Then i connect to closed loop.
    Now i/p frequency Sig In (pin 14) 50 hz,
    VCO o/p is 12.5Khz,
    Vco In VARY 4.1volts to 4.3volts
    feed back Input (pin 3) IS 47.8 hz , Because In feed back path i
    added divide by 256 counter ,

    And The pulse output(PIN 1) goes zero to 5v,like that,i think it MUST
    travel from 5 v to zero volt
    __________ 5v __________
    l l l l
    l l l l
    l l l l
    _____l l__________________________l l 0V



    This is overview of my circuit,

    i want to change the MY 2fl at least 4khz and i expect my f0 at 2
    volts.

    And i changed the R1,C1 value . But i not getting what i expect,
    so plz give some key to open my lock.
     
  14. Andrew Holme

    Andrew Holme Guest

    There is an error in your loop filter design. Your loop is unstable.
    VCO IN should be a flat DC level, and those output pulses should be
    extremely narrow. Your loop is oscillating.

    I also think your tuning range is a bit narrow. You don't have much
    headroom at the top end of the range.

    The reading on your frequency counter is only the average frequency.
    The output spectrum may be centred on 12.5Khz, but there are FM
    sidebands.
     
  15. biras

    biras Guest

    hi
    how can i make sure .The loop filter value is correct.
     
  16. Andrew Holme

    Andrew Holme Guest

    Draw Bode plots of the open loop gain. Adjust the loop filter until
    the phase is well below 180 degrees* at the point where the magnitude
    of gain passes through unity. You will find examples of how to do this
    in books, and on the web, but you need to understand about poles and
    zeroes, transfer functions, complex numbers and the like first. If you
    don't have these basic foundations, your only hope is to download some
    PLL design software, or just fiddle with it until it works.

    * 360 if you include the inversion at the phase detector.
    "well below" = 45 degrees if possible, but less is OK.
     
  17. biras

    biras Guest

    HI
    Thanks for reply

    i know very little bit about bode plot. if u know any good link,plz
    forward to me,so i can try myself.

    Thanking you
    R.Birasanna
     
  18. biras

    biras Guest

    hello
    still now i am fighting with phase lock loop.

    i tried so may way but
    the loop is not stable

    please give some link to find the loop filter value
     
  19. Chris

    Chris Guest

    It's been 9 weeks (June 24th) since you started writing about your 4046
    problem, biras. You've gotten a lot of good advice on this newsgroup
    from many contributors, some of whom (particularly Mr Popelish and Mr.
    Holme) have gone to great lengths (over an hour of their time each, I
    would guess) to help. You've gotten a few very specific solutions
    which you've ignored, as well as considerate general advice and
    specific warnings about what you can do on loop filters without an
    engineering math background which has gone in one ear and out the
    other.

    It's particularly frustrating that you refuse to provide specifics
    about the components of the loop filter you're trying, and haven't
    given a description of what you don't like about the particular loop
    filter you've chosen.

    If you're not technically competent to solve your problem, any third
    year undergraduate EE, or even most any technician with a good math
    background could handle it (or tell you why it can't be done -- many
    loop filter problems are inadmissible of solution) in half an hour or
    so. You might just want to hire somebody to do this.

    I don't think it really matters, though. Repetitive posts which don't
    acknowledge any advice or help that's been given in prior posts or make
    any real effort to communicate clearly qualify as trolling. This
    qualifies. And on the slight chance that this isn't trolling, your
    refusal to communicate your problem clearly despite others' efforts to
    help you put your problem at the bottom of anyone else's list of things
    to do.

    Please go away and bother another ng.

    Or better, why don't you go to sci.electronics.design and try to get
    some help there? I'm sure they'll give you what you need and deserve.
    ;-)

    -------------------------------------------
    Before he could mind, Tom slipped behind
    And gave him the boot to larn him.
    Warn him! Darn him!
    A bump o' the boot on the seat, Tom thought,
    Would be the way to larn him.

    But harder than stone is the flesh and bone
    Of a troll that sits in (newsgroups) alone.
    As well set your boot to the mountain's root,
    For the seat of a troll don't feel it.
    Peel it! Heal it!
    (Biras) laughed, when he heard Tom groan,
    And he knew his toes could feel it.

    Borrowed (with minor modifications) from JRRT
     
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