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Phase comparator gain calculation

Discussion in 'Electronic Design' started by John Wilkinson, Apr 14, 2005.

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  1. Hi,
    I am trying to design a PLL using the 74HCT7046 chip.
    I am using the Phase frequency detector and feeding this into a single
    supply op-amp active PI filter. This has its non-inv input tied at
    vdd/2=2.5V whilst the amp is on +15V to give the VCO tuning voltage
    +2-+15V for a 5MHz change in frequency.

    Now what is the gain of the PD. I have reckoned it as 3*vdd/2pi, is this
    Do I need to take into account that the non-inv input is at half VDD?

    Has anyone got a schematic for a TTL PFD feeding a fast totem pole type
    discrete output at +15V, to up the voltage swing?

  2. Andrew Holme

    Andrew Holme Guest


    When the pull-up transistor is on, the phase detector output voltage w.r.t.
    op-amp virtual-earth is +2.5V
    When the pull-down transistor is on, it's -2.5V.

    If you want to think of it as a voltage-output phase detector, the gain is

    Alternatively, treat it as a current output: Let's say the resistor between
    the PD output and the summing node is R, then the gain is (2.5 / R) / 2pi.
    You now have a current-input active loop filter, of which R is not a part.

    BTW You probably want to split R in two and put a small capacitor to ground
    from the middle. This takes the sharp edge off the pulses before they reach
    the op-amp.
  3. Thanks for the reply Andrew, and sorry for being obtuse, but firstly I
    had the gain for the PFD wrong, it is VDD/4pi.
    Are you saying that now I have the split supply to the op-amp this is
    now doubled? ie 2*vdd/4pi.

    Many thanks,
  4. Andrew Holme

    Andrew Holme Guest

    No. The PFD gain is not affected by the op-amp power supply.
  5. John Larkin

    John Larkin Guest

    The charge-pump pd's are generally loaded into a capacitor, and the
    chip output is usually considered to be a current source. So the
    transfer function from phase to pin voltage is of the form k/S, an

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