PGA4311 bypass caps

[CommanderLake]

Heres the datasheet: www.ti.com/lit/ds/symlink/pga4311.pdf
Look at page 11 figure 5, could somebody please clarify the placement of the bypass capacitors on this IC, theres a 0.1uF on the left side + and - and on the right side theres a 0.1uF on just the negative but connected to the digital ground pin?

 

[duke37]

What is the problem?

The capacitors should be connected from close to the chip to a good ground plane, there is a layout earlier in the document which I have not looked at.

 

[CommanderLake]

Look at C12 on the right why is it there and why is it connected to the digital ground why is it closer to the digital ground why is there no positive capacitor on the right, I would use PP film for the 0.1µF caps is this ideal?

 

[duke37]

C12 is not necessarily closer to the digital ground, this is a circuit diagram, not a layout. Layout and capacitors will be critical to minimise digital interference on the analog signal.

I presume p7 and p22 are internally connected.

I think that any good capacitors would do.