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Performance of IC

Discussion in 'Electronic Design' started by Julian, Sep 11, 2004.

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  1. Julian

    Julian Guest

    In chip design I have a question about scaling the supply voltage VDD.
    On some sites I can read that the transition time from e.g. high-to-low on a
    CMOS transistor output, lets call it tpHL, decreases as VDD is increased.
    This I can imagine as there apparently would be more charge available, hence
    load capacitances would be charged faster -> faster tpHL.

    Other places I read that decreasing the swing-voltage, that is the voltage
    swing (e.g. lower from 5V to 3.3V) would decrease the tpHL. This I can
    imagine as less charge has to taken from the supply lines in order to charge
    the load capatitance to a logic level. But......is'nt this a paradox??? What
    am I missing? Am I mixing things up?

    Please help the confused VLSI newbie......
    Best Regards
    Julian
     
  2. If the device already exists. i.e. its already designed with a given
    process. Increasing the voltage usually reduces propagation and
    rise/fall times, becuse it increases the current/gm. If you redesign the
    process so that it uses a lower supply more effectively, then it will be
    faster with that lower voltage.

    Kevin Aylward

    http://www.anasoft.co.uk
    SuperSpice, a very affordable Mixed-Mode
    Windows Simulator with Schematic Capture,
    Waveform Display, FFT's and Filter Design.
     
  3. legg

    legg Guest

    Basic limitation is on resistance of the mos structure. Node
    capacities are discharged using this R value. As VDD increases, the
    gate enhancement increases, reducing R and increasing speed. Power
    loss increases to CV^2, however.

    Voltage swing is typicall dependant on VDD, unless internal
    subsections operate off internally regulated supplies.

    R is typically process-related. So is the operating voltage limit.

    RL
     
  4. John Larkin

    John Larkin Guest

    All the CMOS logic I've seen gets faster at higher voltages. There's
    just a lot more gate drive, hence more available drain current, to
    charge internal nodes.

    They get faster at lower temperature, too.

    Some of the TinyLogic and LVDS parts can switch 6 volts in something
    like 400 ps.

    John
     
  5. Joerg

    Joerg Guest

    Hi John,
    Some lower voltage stuff can be impressive, too. The 74AUC chips boast a
    prop delay of 1.5nsec even when operated under 2V.

    Regards, Joerg
     
  6. John Larkin

    John Larkin Guest


    Yeah, who needs 10KH when you can get a Tiny cmos flipflop with 1 ns
    prop delay? Such toys we get these days!

    John
     
  7. Joerg

    Joerg Guest

    Hi John,
    Best of all, you don't need to call the utility anymore before you turn
    on your prototype. No more 5V 100A power supplies needed. If designed
    right you can run this stuff on a couple of AA cells all day long.

    The downside of all these nice chips is that many, if not most, young
    engineers coming out of college don't know how to design down to
    transistor level anymore. Many never get there even after years on the job.

    Regards, Joerg
     
  8. Ban

    Ban Guest

    But hasn't been that always been the case with digital designers? And more
    so with "softies"? As long as there are us dinos around who solve their EMI
    problems, so what? But what will happen when we are gone? Back to stone age?
     
  9. Joerg

    Joerg Guest

    Bongiorno Ban,
    Kind of. I suspect lots of problems will remain unsolved.

    In the old days, meaning about 20 years or so ago, even our SW engineers
    knew how to use a scope and a logic analyzer. Even how to get the stuff
    to trigger right. But these folks are now in their 50's. Of the new
    generation many become completely frazzled with scope. One guy was
    really close to desperation until he finally asked us HW guys. He had
    the trigger on the wrong channel the whole time...

    But let's not complain. The situation is the same with other technical
    tasks. Remember when we whipped out the car jack and crank after a flat
    tire happened, without much hesitation? Nowaday all they do is crack out
    the cell phone.

    Ciao, Joerg
     
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