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PCBs and Grounds

Discussion in 'Electronic Design' started by Paul Burridge, Jan 19, 2004.

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  1. Hi,

    I'm about to start making up another board for the field-strength
    meter and there's an obvious question here that I need answered before
    I start - in the interests of not making another balls-up.
    Everyone says to make the ground on the board the dominant area.
    That's self-explanatory with one power lead in and one ground wire.
    But what if it's a *split* supply? Does this spacious area then have
    to become connected to the -V of the supply does it go to the
    middle/'nuetral' of the supply.
    I'm just unsure as to whether it remains ground in this instance or
    whether it must be connected to the 'lowest voltage' source which
    would be the minus supply lead.
    That's not terribly well explained but I hope you get my drift...
     
  2. j.b. miller

    j.b. miller Guest

    It goes to the 'ground/neutral as you called it, NOT the -v.

    As well, I've had better luck creating ground planes consisting of x-y
    stripes as opposed to 'solid fill'. The actual lines were 50thou wide, about
    200 thou spacing. Started this technique after designing optical emission
    spectrometer interfaces.
    Also helps to keep the board roughly square or slightly rectangular, why?, I
    don't know, just worked for me.

    jay
     
  3. Leon Heller

    Leon Heller Guest

    It's ground, the little triangle symbols on the schematic, like those on
    the bases of Q1 and Q2 or the mid-point of the supply.

    Leon
     
  4. Bob Stephens

    Bob Stephens Guest

    I used to do this in the old days when large copper pours were apt to cause
    bubbles under the copper during etching. I still kind of like the
    crosshatch look. Does anyone know how this affects the properties of a
    ground plane? ie solid versus grid.

    Bob
     
  5. John Larkin

    John Larkin Guest

    For fast stuff, use double-sided copperclad and leave the bottom side
    solid as the ground plane. Put parts and traces on top, and punch vias
    or via jumper wires down to the ground. Topside copper pours are OK,
    but if they're not very firmly strapped together they can do more harm
    than good.

    Live bug construction - hand-wired on a piece of plain copperclad,
    chips with their nongrounded little feets bent out parallel to the
    board - works very well for simple circuits.


    The basic rules for high speed design are

    1. Keep all interconnections zero length

    and

    2. Keep the parts far apart so they don't interact.

    so some juggling is clearly required.

    Actually, at 40 MHz, things shouldn't be that bad. Your circuit
    actually has modest gain, so shouldn't be terribly picky.

    John
     
  6. Paul,
    The GND plane has nothing to do with the potential.
    It is what all signals a referenced to.
    This means in case of a dual supply (+-15V), 0V.

    Rene
     
  7. I only do analog stuff; not interest in switching. Beyond what
    frequency would you say double-sided board with one side as ground
    becomes essential?
    So you're saying that it's better to have long interconnecting
    *tracks* on the board than long component leads?
    One obvious point bugs me here: keeping the parts far apart is
    desirable to prevent interraction, but how the hell is this possible
    in IC design????
     
  8. John Fields

    John Fields Guest

    ---
    John, you sly dog, you've sent him after the Holy Grail!!!^)
    ---
    ---
    It isn't!-)

    Some guidelines:

    1. Make the area of ground as large as possible.

    2. Make your power supply traces as wide as possible.

    3. If you can't think of a reason why not to, decouple.

    4. Don't run inputs and outputs physically in parallel with each other.

    5. Don't run inputs and outputs close to each other.

    6. Don't run inputs and outputs next to each other.

    7. If you have to run inputs and outputs next to each other, put a
    ground trace between them.

    8. Keep opamp and comparator input components as close to the package
    as possible.

    9. Opamp summing junctions are your enemies; make sure that resistors
    which are feeding them are as close to the summing junction pins as
    possible. This is where zero-length matters.

    10. If you have a choice between mounting components closer to outputs
    they're connected to than inputs, mount them closer to inputs.
    If you don't have a choice, move things around until you do.

    11. Mount inductive components away from or at right angles to each
    other's winding axis.

    12...
     
  9. I'm just wondering how exactly doing this improves things. What's the
    reasoning behind it?
    What, between supply and ground? If I end up with say 10 of these .01u
    caps in a larger design, then they'll parallel up to .1 surely? Or is
    that only at LF and DC? Not that it matters between supplies and GND,
    I suppose...

    [Rest noted]
     
  10. Because the inductance of a wide trace is less than that of a skinny trace.
    (That's also partly why ground planes are good. And it's why, in radio
    transmitter facilities, big flat bands of copper sheet are used for
    grounding, rather than using thick copper wires.)

    Between ground and anything that should have zero AC impedance to ground,
    such as the supply pin of an IC.

    At RF, a trace looks like a resistor. (It does at LF, too, but not as big a
    resistor.) Pick somewhere on your circuit that looks, on the schematic,
    like it's connected to V+. Now redraw the schematic to add a resistor
    there. Does the circuit still work as well? You'll probably find that
    you've introduced distortions, oscillations, gain loss, etc. If so, then
    that point needs to be decoupled to the ground plane.

    I believe it's called "decoupling" because otherwise, the voltage at the
    point of interest is coupled to the signal.

    Two 0.01uF caps in parallel has a smaller effective series resistance than
    one 0.02uF cap would. And a 0.01uF cap right next to a component is much
    better at decoupling than a 0.1uF cap a couple of inches away would be,
    because of the inductance of the trace between them.
     
  11. Thanks, Walter. I suspected it was something like that.
    Yes, that all makes perfect sense. I can't understand why the books
    seem so thin on detail on this important aspect of actually making
    designs *work*. I have a copy of 'The Practical RF Handbook' which has
    loads of very useful data in it, but *nothing* about layout and
    decoupling! Quite a serious omission for a book claiming to be a
    "practical" guide!
     
  12. John Fields

    John Fields Guest

    ---
    It's twofold in that if you don't have, everywhere, a stable reference
    for zero volts (ground) then you can't predict what effect your signal
    will have on the output you want. For example, let's say that you have
    a comparator with one input sitting at a voltage referenced to ground
    and the other input set to switch at 1 volt. If the reference's ground
    is moving around because it's sitting on a ground which varies from
    -10mV to +10mV, then its output is going to be moving around as well,
    and you won't be able to tell whether the comparator's output is
    switching at 990mV, 1010mV, or anywhere in between. If you have a
    massive ground, then when currents are drawn through it the voltage
    drops across it will be small because the resistances between the points
    where current are flowing will be small, and the voltage drops due to
    the currents flowing through those resistances will be small.

    Likewise, if you have, say, a chip which is drawing a large current from
    the supply and it has a high-resistance path to the supply because of
    narrow power supply traces on the PCB on which it's mounted, then the
    voltage dropped across those traces will not be available to the chip
    for it to do what it's supposed to do.
    ---
    ---
    Yes, but _where_ you decouple supply from ground is more important than
    just blindly throwing caps around.

    The aim of decoupling is to fool everything on the PCB into thinking
    that it's so important that it's connected to its own infinitely
    compliant power supply, and that's done by placing a device (a
    capacitor) capable of storing the energy the device (the chip) needs to
    function properly, short term, across the supply terminals of each chip
    which needs help. By doing that, the instantaneous high-current needs
    of the chip will be supplied by its own capacitor reservoir instead of
    the primary supply and the horrible power supply wiring leading up to
    the chip, and when the needs of the chip subside, the capacitor will
    charge up for next time through the wiring which now doesn't look so
    bad...
    ---
     
  13. Quack

    Quack Guest

    I just have to say that this was a very meaningful post for me.
    I have been told by a few people to use decoupling capacitors
    throughout my pcb's - i usually omit them - having never yet seen a
    problem that i believed was related.
    But only now does it begin to make sense ..

    Thanks :)

    Alex.
     
  14. On Mon, 19 Jan 2004 21:19:32 -0600, John Fields

    [snip]

    Thanks, John. You do explain these technicalities with remarkable
    clarity, I must say. The more I learn about this subject, the more I
    realise my original board layout for the FSM was totally hopeless and
    doomed to fail. I'm going to start another one today implementing all
    the suggestions that have been made and hoping for rather better
    results...
     
  15. The name of the book is "The Practical RF Handbook", not "RF for
    Idiots".
     
  16. JeffM

    JeffM Guest

    Take a bow, John. Explained as well as ever I have heard.

    With the occasional calls we see for a FAQ (most recently by Activ8),
    this is a good one to bookmark for inclusion, verbatim.

    We can call it Why Ground Planes and Bypass Capacitors?.
     
  17. Now that John made a splendid cake, allow me to add some icing to it...

    The effectiveness of decoupling capacitors has - oddly enough - a lot to
    do with inductance. Stray inductance, that is. That is the inductance of
    the wiring connecting the capacitor to the power consumer. Say the power
    consumer is an IC with a ground pin and a power supply pin.

    An inductor, remember, wants to keep the current through it constant. If
    you attempt to change the current, the inductor will develop a voltage
    to counteract this. The net result is that you can not change the
    current instantaneously.

    Compare that with the behaviour of a capacitor. A capacitor wants to
    keep the voltage across it constant. If you attempt to change the
    voltage, the capacitor will develop current to counteract this.

    So if your IC (the power consumer) consumes constant current, you don't
    need any decoupling, as the stray inductance has no effect. If, however,
    the current varies over time, the inductance will counteract this. If
    the IC wants to increase its current consumption, the inductance will
    develop a voltage to counteract it, meaning it will reduce the IC's
    supply voltage. If the IC wants to reduce its current consumption, the
    inductance will correspondingly increase its supply voltage.

    The IC's supply voltage, that is the voltage between its power supply
    pin and its ground pin. Or, more precisely, the voltage between its
    power supply pads and the ground pad. Pads are the connections on the
    silicon chip itself. The pins are connected to the pads using wires
    inside the chip package, so there is some inductance already between pad
    and pin. When very fast current changes are involved, this little
    inductance matters, too.

    It goes without saying that those changes in a chip's supply voltage are
    bound to disrupt its desired operation once they exceed a certain
    margin. The actual margin depends on the situation, of course, but in
    nearly all cases it will matter to some extent.

    The wiring inductance between our IC and the power supply is bound to be
    fairly high. This is unavoidable because the power supply will be at
    some distance from the power consumers. The cure is therefore to provide
    some local "interim" power source that is not affected by the wiring
    inductance. This is what bypass capacitors are doing. For their
    effectiveness it is essential that the inductance between them and their
    respective power consumer is minimal.

    Actually it is the inductance *and* the resistance that need to be
    minimized, because both reduce the effectiveness of the bypass
    capacitor. The resistance is easier to deal with than the inductance,
    though.

    So what can we do to reduce the inductance? You need to be conscious of
    what causes it. A straight wire already has inductance, so you want to
    reduce wire length. A wire loop has an inductance that depends on the
    loop area, so you want to reduce the loop area. If you can not make the
    loop shorter, you can still reduce the area by running the wires close
    to each other (the wire to and the wire fro, that is). Besides reducing
    the inductance, that also has the effect that less energy is radiated
    into space (the loop is also an antenna).

    So proper placement of a bypassing capacitor for our IC would be
    straight across its power supply pins, so that the loop formed by the IC
    and the capacitor circumscribes a minimal area. If you're doing a PCB,
    you want to arrange the wiring on the PCB so that this situation is
    approximated as well as possible.

    Of course, a real world circuit has such a lot of power consumers that
    it would amount to a lot of work to figure out what all the loops are
    like and minimize them. Enter the ground (and power) plane. If the wires
    are actually planes, as in a multilayer PCB, you do not need to figure
    out the loop areas for all possible currents, as the currents
    automatically choose the path of least impedance. Note my switch of
    terminology from inductance to impedance. In the DC case (currents are
    constant) the impedance is equivalent to the resistance. DC currents
    therefore choose the path of least resistance. At higher frequencies
    (alternating currents) the inductance gains more and more prominence, up
    to the point where resistance does not matter anymore.

    So a power plane allows the currents to choose the best path themselves,
    for *any* frequency. So while a plane is not really *necessary*, it
    saves you a lot of work figuring out all the loops in order to minimize
    them.

    For example, if you have a ground plane and above it a power wire
    zigzagging about. A DC current will now choose the direct path in the
    ground plane. A high frequency current however will zigzag in the ground
    plane in parallel to the power wire, because that yields the smallest
    loop area. By having a ground plane you allow this to happen. If you had
    a single ground wire instead, you would predetermine the current path
    (and thus the loop area) for all frequencies.

    Cheers
    Stefan
     
  18. On Tue, 20 Jan 2004 20:38:41 +0100, Stefan Heinzmann

    [interesting explanation snipped]
    Thanks, Stefan. I never realised there was so much to this.
    I've come across ICs that have power and ground connections diagonally
    opposite each other so they are at the furthest pins apart! How is one
    to effectively mount a capacitor when the relevant pins are placed in
    the most difficult position WRT minimising lead length for the bypass
    cap??
     
  19. You're probably referring to digital logic ICs (i.e. 74xx series).
    You're completely right, from the bypassing viewpoint the position of
    power supply pins is about the worst they could choose. As the logic
    families gradually became faster this problem became apparent. The
    traditional arrangement of power pins is called "corner pinning". There
    have been attempts to replace that with different pinouts that have the
    power supply pins in the center of the pin rows either side of the
    package, but it didn't catch on, probably because it confused PCB
    layouters ;-)

    Of course, the general trend towards smaller packages mitigates the
    problem. The trend is towards packages the size of the chip itself. For
    example, the chips can have solder bumps directly where the pads are, so
    that there's no extra wire needed to bond it to a pin. The pad gets
    soldered to the PCB directly. This is probably the connection method
    with the least inductance, hence most suitable for high speed stuff.
    Breadboarding gets tricky, though ;-)

    Cheers
    Stefan
     
  20. If you have a ground plane, use it.

    An IC is not a magic box that has power supply pins and inputs and outputs.
    It's a circuit, and all those pins are internally connected in some way such
    that currents flow from one to another and voltages from one to another are
    sensed or produced.

    At any given moment, for any given output, it is *either* drawing current
    from the supply pin and sourcing it through an output, *or* sinking current
    from an output into ground. Either, neither, or both of those might disrupt
    its function. When it pulls current from the supply pin, if that causes the
    voltage at the supply pin to drop, that could (or not) cause a problem.
    When it stops pulling current from the supply pin, if that causes the
    inductance of the supply lines to generate a voltage spike, that could (or
    not) cause a problem. When it sends current from the output into ground, if
    that makes the ground voltage rise with respect to the supply or to an input
    or another output, that could (or not) cause a problem. And so on. These
    are all separate problems, with possibly separate solutions.

    You're not trying to decouple the Vcc pin of the IC to the ground pin of the
    IC, you're trying to decouple it to *ground*. The voltage between the Vcc
    pin and the ground pin of the same IC is probably no more important than the
    voltage between the Vcc pin and, say, the ground reference of the next IC.
     
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