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PCB layout for ADC

Discussion in 'Electronic Design' started by [email protected], Jun 30, 2006.

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  1. Guest

    Hi everyone

    I recently joined a (small) company that has a very high end A/D system
    using four 16-bit A/D channels. Two of the channels have a gain of 128
    or even more so they can be quite sensitive.

    We were using the Burr-Brown DSP102's but they are terribly obsolete so
    we are forced to design a "daughterboard" to plug into the through-hole
    pins until we finish redesigning the board. We chose the Analog
    Devices AD977A as the replacement.

    I did not design the original PCB's and that's not my expertise, so I
    have a couple of key questions:
    1. When connecting the power rails (+5V, -5V, and GND) of the
    daughterboard to the main board, should we use only a single pin or
    multiple pins? My instincts tell me that we should treat it as a
    "star" grounding system and not introduce any loops, so we should only
    use 1 pin for each of these nodes. But any thoughts are very welcome.

    2. We are doing a 4-layer board with GND on layer 2 and the power on
    layer 3. For power, we're thinking to do a pour of +5V_analog and then
    run thick traces for +5_digital and -5V as necessary. Is this okay or
    should we try to do more of a "plane" style with larger areas for the
    "minor" rails? BTW, the -5V is not for the A/D, but for an op-amp
    buffer that maintains the voltage reference.

    3. Any thoughts on doing GND copper pours for the top & bottom layers?
    The previous design did not use any copper pours for the routing

    4. The main board already provides "bulk" 10 uF caps for the power
    rails. Should we add 10uF caps onto the daughterboard as well or just
    not worry about it?

    FYI--we have a single discontinuous clock line running AFTER conversion
    at 10 MHz. There is also a CONVST pulse (0.1us wide) to start
    conversion. The analog signals range from 30-450 kHz.

    We already bought Howard Johnson's "High Speed Digital Design" which is
    supposedly the end-all & be-all of PCB layout, but I would say that PCB
    layout for A/D's is one of the trickier topics and it's not clear how
    to apply those principles to "low speed analog design" :).

  2. John Larkin

    John Larkin Guest

    Use lots of ground pins.
    Ground plane for sure. Power runs can be fat traces or planes. If
    planes, you might put analog planes on the opposite side of the ground
    plane from digital power.

    One inner-layer ground plane should be enough. Surface fill-in pours
    are mostly cosmetic.
    Better to use surfmount ceramics, close to the adc power pins, 0.33 uF
    maybe. The ADC ref bypass cap should be local, too.
    Since this ADC has a single-ended input, ground noise is going to be
    an issue. If the board is quiet before each ADC shot, that will help a
    HoJo's book is half good stuff and half nonsense.

  3. Guest

    I agree. What do you think of Tom Van Doren's material though?
  4. John Larkin

    John Larkin Guest

    Haven't seen his stuff. Got any references?

  5. Joerg

    Joerg Guest

    Hello John,

    16 bit converters of this caliber should be treated like "high speed
    Hmm, I tend to recommend it to clients who ran into termination issues
    and things like that. What didn't you like about the book?
  6. Guest

    1. When connecting the power rails (+5V, -5V, and GND) of the
    Make cluster of gnd/Vcc pins adjecent to eachother?

    Maybe this doesn't apply. But inductor between digital and analog power
    supply Vcc seems to help (when they draw power from same "outlet").
    Small decoupling capacitors near consumer(s) proberly doesn't hurt.

    Maybe shielding could help?
  7. Andrew Holme

    Andrew Holme Guest

    Linear Technology have an interesting application note AN71 entitled "The
    care and feeding of high performance ADCs: Get all the bits you paid for"
    which addresses the issues you mentioned. Google for: linear technology
  8. John  Larkin

    John Larkin Guest

    Well, there's an average of about one factual error or insanely
    fatheaded remark per page, starting on page 1, where we learn that few
    electrical parameters remain constant over a span of 20 decades in
    frequency, provided that we use a log scale.

    Did you know that the risetime of a type N connector is 4 picoseconds,
    and a foot of RG-8 is 200 fs?

    His ideas about bypassing, and his obsession with return currents, are
    just silly. Can anybody make sense of page 273? Page 261 is insane,
    "An interesting consequence..." and "At the point...". And the 5 rules
    starting on that page are plainly crazy... nobody does this; well, #4
    isn't so bad, assuming multiple ground planes, which is a whole nother

    P279, we learn the startling fact that "Combining TTL and ECL in one
    system without considering the system design consequences is not a
    good idea." Oh, please. Bullet 4 below is crap.

    Really, there are too many to list. But if you give me a random page
    number, we can find a few nearby absurdities.

  9. Nico Coesel

    Nico Coesel Guest

    Just make sure the analog and digital ground currents don't get mixed
    (this is not trivial in many cases) and the analog and digital suppy
    are well seperated (using independant supplies or LC filters). Using
    pours is usefull for spreading heat and/or creating a (tiny) capacitor
    together with the ground plane.
  10. That's a good pointer and a nice little appnote - short and to
    the point. I had a question about their recommendation that you
    can benefit from using both an analog and a digital ground plane
    on two separate layers.

    Wouldn't the capacitive coupling stuff things up?

    Also re someone's suggestion of using an inductor to couple the
    two planes. Is this a good idea in the layout LT show, and what
    inductance might you be looking for?
  11. Joerg

    Joerg Guest

    Hello John,
    Well, at least our mains supply remained nearly constant after the last
    governor was kicked out :)

    Maybe he assumes that everybody has a defense-style budget and
    everything is rigid coax.

    "Liz has designed...". Yeah, I always wondered who Liz is. This way of
    calculating the bypass cap budget is indeed a bit odd. I just do that
    with charge calcs.

    Rule #4 would also apply to a common ground. I have seen many boards
    where the number of ground vias was so paltry that I had to drill and
    jumper to demonstrate to a client how to make it work (initially they
    didn't believe it).

    Agree. Splitting power planes can at times be as bad an idea as
    splitting grounds.

    I guess you are right. But we can't judge the book from the position of
    a seasoned engineer. To us those kinds of books often appear to talk the
    obvious. Until the next consulting trip comes, you look at someone's
    design and realize that it ain't quite so.

    Most readers, at least the ones to whom I recommended the book, don't
    have our experience and tend to make rather blatant mistakes. Split
    planes, bypass caps out at sea, non-terminated clock lines and so on.
    For them it should still be a good read unless there is a better book. I
    haven't come across one. But then again the EE section of our local
    Border's store has now shrunk to less than 3ft of shelf length. Sigh...
  12. John  Larkin

    John Larkin Guest

    With some intelligent editing, it could have been very good.
    Yeah. Our nearby Borders has a huge, room-size "computer" section that
    has not a single book on PC hardware. You can buy the (something like)
    6-volume, 10k page shrink-wrapped ".NET Foundation" set for $450.

  13. Joerg

    Joerg Guest

    Hello John,
    Agree, the writing style needs some polishing.
    I noticed that .net heaviness. Sad. I think they are pricing themselves
    out of some markets. Win's AoE book was a whopping $90 there. Ouch. I
    had purchased the 2nd edition just when it had come out at Tower's for
    $49.95. You can still buy it around that so I don't know what their
    marketeers are thinking.
  14. Guest

    Well, at least our mains supply remained nearly constant after the last
    Maybe talked so much the wires were energized ;)
    What happends in the splitted powerplane setup ..?
    Less books => Less competition => More business ? :)

    Software is nice, but if it can't interface to reality it's hardly going to
    make a real difference..
  15. JeffM

    JeffM Guest

    Well, at least our mains supply remained nearly constant
    Pretty sure that the Feds arresting Kenny Boy & his band of thieves
    had a bigger impact on the situation.
  16. Joerg

    Joerg Guest

    The same stuff that happens with split ground planes, for example that
    your assessment of what behaves digital and what behaves analog isn't
    corroborated by the actual circuit. AD converters can be particularly
    nasty here. If you at least have one common ground plane and bypass well
    things might still be ok though.
    True, currently I have no idea who is going to fix serious noise issues
    50 years from now.

    That's what all the hotshot dot-com "web portal designers" realized when
    their paychecks stopped coming.
  17. Joerg

    Joerg Guest

    Hello Jeff,

    It had an impact but the main mistake in those days was that utilities
    were prevented from signing long term contracts. That was IMHO rather
    stupid. Every properly run enterprise hedges against all kinds of
    fluctuations. Energy, exchange rates, raw materials, you name it. Yet
    politicians appear to have taken it upon themselves to think that wasn't

    Luckily this is now behind us.
  18. JeffM

    JeffM Guest

    Well, at least our mains supply remained nearly constant
    Your point is valid, but you're talking about
    making rules for folks who didn't feel bound by rules.
    Pretty sure the rolling blackouts were completely artificial.*-smartest-*-in-the-room+artificial-shortages
  19. 1 pin for each would be the way to go, but if you are designing a
    plug-in daughter board then you have to be careful where that "ground"
    pin goes on the main board.
    If you have mixed digital and analog grounds then you have to be extra
    careful and keep them seperate.
    Without full details of your system it's hard to say for sure.
    Forget planes for the rails unles you have clearly delineated analog
    and digital sections. Use one plain for GND as you already have, run
    the power rails as thick traces on the other inner layer, and then
    copper pour around the power rails on that inner layer also. Remember
    to stitch the grounds together too.
    Generally a good idea, although it may or may not actually do anything
    for you, but hey it looks good though ;-)
    If you need seperate analog and digital grounds then it's probably best
    left off, unless you know the specifics and you want to copper pour
    around your analog section only for example.
    Don't worry about it. High frequency bypass caps should be sufficient.

    The key to A/D board layouts is keeping your analog and digital grounds
    and sections as physically seperate as possible. Really high end 24bit
    sigma-delta converters for example will have one side of the chip
    package with all the analog pins and the other side with all the
    digital pins to aid in such layouts.

    Dave :)
  20. Guest

    You should read carefully all the reference designs provided by the ADC
    I guess your company has signed a NDA with that company so, you should
    have all
    There isn't a single rule for all ADC about separating analogic and
    digital ground, even this is a common issue. Some ADC manufacturers of
    fast ADCs, requires a clock which usually is treated as analogic clock.
    (see fast ADC from Maxim). This clock is the biggest
    perturbator on the board.

    Ground plane or fragmented ground plane on the routing layer is usually
    Multiple vias will connect the ground planes on all layers.
    Worry as well. 10uF + 100nF +10nF +1nF is one example where the
    datasheet must be readed carefully. Choose a combination with an
    equivalent lowest ESR on the whole frequency range, covering at last
    the third harmonic of the biggest perturbator (ie sampling clock).
    Is not clear even in practice. One trick is to design 0 resistor
    between various ground planes in various positions on the board and
    just check the effect.
    Noise simulation is usually useless.

    Vasile Surducan
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