PCB Layout Designers

[David L. Jones]

How do you handle data sheet revisions? Some, particularly
semiconductors, tend to have a number during the life of the part. Do
you attach multiple datasheets if there are multiple vendors?

Best regards,
Spehro Pefhany

 

[David L. Jones]

How do you handle data sheet revisions? Some, particularly
semiconductors, tend to have a number during the life of the part.

We generally overwrite the linked datasheet with the latest revision.
However if there is a reason to keep multiple datasheets then we can
add as many linked documents to a part as we want, labeled
appropriately (datasheet-Rev1.pdf etc ). This includes app notes too.

Do you attach multiple datasheets if there are multiple vendors?

Yes, we do that, and we can also have a selection of footprints for
the same device and have it associated with a different ordered part.

It's fantastic having a built up library of components all with linked
datasheets, app notes, multiple footprints, purchasing info etc, makes
future designs real easy. What's more, basic parametric info is also
included with each part, so you can often select a suitable device
from the library without even having to view the linked datasheet, and
you can sort lists of components by any parameter to make it even
easier.

Dave.

 

[John Larkin]

We operate in different worlds, John { >

(snip)


I wonder how many do autoroute at both your level and down here at the base
where I operate. The tools are there, but I don't think it is ego that stops
most layout people lwetting the autorouter have a go.

Autorouters don't have strategies, like people can, so start at a huge
disadvantage. They often make such a mess of a board that it takes
more time to clean it up than it would have taken to do it manually.
Not to mention the unbearable ugliness most autorouters create.

I'm surprised that you don't accommodate gate swapping. Assigning a gate from a
package at schematic time is an arbitrary thing, and can't second-guess which
gate will provide the best layout.

We do usually force sensible package sharing at schematic entry
(proper halves of a dual opamp, say) when that makes sense. We usually
have a rough channel placement or whatever in mind. If we have, say, a
bus connector that goes to a 16-pin bus transceiver, we will assign
the pins that we know will line up nicely. This is *not*
throw-the-schematic-over-the-wall methodology. We'll sometimes meet
and plan a layout strategy, and sometimes change the design if it
looks like that will help.

If my layout guy has a real problem, he can come to us and we can
alter the schematic to help. But on a multilayer board, you don't have
the crossover dilemmas that you have on a 2-sided board, so pin/gate
swapping isn't as crucial.

John

 

[Spehro Pefhany]

We go a few steps better with Altium Designer and make sure every part
in our library has the full datasheet attached to every component,
along with a physical 3D model, and all the required manufacturing and
sourcing details. It's a lot of work up front, but it really pays
dividends when you can simply hit a button and generate full
manufacturing and purchasing BOM's and *know* it's all correct.
Datasheet linking is like having a scrolly-wheel mouse, once you've
used it you never want to go back.

Dave.

How do you handle data sheet revisions? Some, particularly
semiconductors, tend to have a number during the life of the part. Do
you attach multiple datasheets if there are multiple vendors?



Best regards,
Spehro Pefhany

 

[Robert Latest]

PADS will do a full connectivity check on this
board in about 2 seconds

What's a connectivity check? I guess it's checking that all power pins are
connected, that there are more than one pins on one net, that no two outputs
share the same net, that a net not only has inputs on it, no open inputs...
that sort of thing? It's called "electrical rule check" in my CAD.

You can also resequence the ref
designators on the board

What's a "ref designator"? The "name" of the Part, such as U22, R4?

We never autoroute,

Ugh. Who does, anyway?

robert

 

[John Larkin]

What's a connectivity check? I guess it's checking that all power pins are
connected, that there are more than one pins on one net, that no two outputs
share the same net, that a net not only has inputs on it, no open inputs...
that sort of thing? It's called "electrical rule check" in my CAD.

It's a full check of the pcb connections against the schematic
netlist. That's a little more extensive than what you describe.

What's a "ref designator"? The "name" of the Part, such as U22, R4?

The "R4" is what we call a "reference designator". Each part can have
other attributes, like

type = RES/0805
value = 10K
HTI# = 17213 (our stock number)
decal = 0805

Ugh. Who does, anyway?

I guess some people do. Hell, routing is too important to be left to a
machine.

John

 

[Robert Latest]

It's a full check of the pcb connections against the schematic
netlist. That's a little more extensive than what you describe.

Ah I see. I was unaware of that because what I use (cheap EAGLE) does it
implicitly.

I guess some people do. Hell, routing is too important to be left to a
machine.

Especially if you're as anal about the aesthetics of the result as I am
(and from what I've heard you say, you too).

robert

 

[SioL]

Especially if you're as anal about the aesthetics of the result as I am
(and from what I've heard you say, you too).

robert

I even care about the colour of say thru-hole "folien" caps, sometimes you have
a choice. Its almost sick when you're prepared to pay a tiny bit more to have
the better looking colour, than again some customers do appreciate that

SioL

 

[John Larkin]

I even care about the colour of say thru-hole "folien" caps, sometimes you have
a choice. Its almost sick when you're prepared to pay a tiny bit more to have
the better looking colour, than again some customers do appreciate that

SioL

We sell VME boards, where all the parts are in plain sight... no
enclosure. So we care a lot about the beauty of the board: colors,
placement, lettering, trace flow. It's art.

John

 

[SioL]

We sell VME boards, where all the parts are in plain sight... no
enclosure. So we care a lot about the beauty of the board: colors,
placement, lettering, trace flow. It's art.

John

There's true beauty in a nicely laid-out board.
I guess that makes us certified geeks.

SioL

 

[David L. Jones]

We sell VME boards, where all the parts are in plain sight... no
enclosure. So we care a lot about the beauty of the board: colors,
placement, lettering, trace flow. It's art.

If for aesthetics or some other reason you want to hide the trackwork
then black solder mask is the way to go. Looks more like a finished
product than a bare PCB. Very nice when combined with copious amounts
of gold flash.

Dave.

 

[Haude Daniel]

We sell VME boards, where all the parts are in plain sight... no
enclosure. So we care a lot about the beauty of the board: colors,
placement, lettering, trace flow. It's art.

Absolutely. I often do mechanical design as well, and the same rules
apply. Even when the device in question is eventually buried in some
vacuum chamber and (ideally) never sees the light of day again. I
think things that look shitty can't work well: Good looks don't
necessarily imply high functionality, but if something turns out to
be crap after all -- well, at least it looks good. As long as you
never compromise functionality for beauty, I've found this to be a
good design strategy. And the mech workshop loves you if you turn
in beautiful drawings for beautiful things.

For my latest electronic gadget, see

http://www.nanoscience.de/group_r/members/dhaude/sed/stm-amp.jpg

Part density is very low, but there's an equal amount of stuff (power
supplies, 4000B series control logic, relays) on the bottom. Piggy-
backed and missing components betray the prototypiness of the thing,
as do the almost-non-overlapping mounting screws.

The front panel is CNC milled from red anodized aluminium:

http://www.nanoscience.de/group_r/members/dhaude/sed/front-panel.jpg

Note the holes for accessing the recessed M5 mounting screws which
firmly bolt the device on a UHV flange. The "4mm hex" designation is
pretty tacky and cost me a couple Euros extra, but without it the
holes had an unmotivated look to them that I didn't like.

--Daniel

 

[SioL]

If for aesthetics or some other reason you want to hide the trackwork
then black solder mask is the way to go. Looks more like a finished
product than a bare PCB. Very nice when combined with copious amounts
of gold flash.

Dave.

AND its much harder to copy your design. Just one of the things that puts the thieves
off.

SioL

 

[vasile]

We recently did a board that has over 1000 parts, including a uP and
two FPGAs, 8 layers, parts on both sides. Hand checking that would
probably take two people a week or so, one calling out connections and
the other tracing them. PADS will do a full connectivity check on this
board in about 2 seconds, and a full design-rule check in under 10.

And depending what you have previously done (like autorouting a class
of signals
with some impedance restrictions and accordeons generation) will
forgot or not to number the ground connections on planes. Which
omission will be kept till finishing the board...
Pads (2005) is as buggy as any other CAD, maybe you are lucky ?

We never autoroute, and almost always go with the pins as originally
assigned on the schematic, ie no pin or gate swapping.

I'm wandering how you're routing 1000 components (saying you have at
least two 1200 balls BGA's on board and every of them with 300
filtering capacitors) and 10-14 layers without autorouting ?

thx,
Vasile

 

[Robert Latest]

I'm wandering how you're routing 1000 components (saying you have at
least two 1200 balls BGA's on board and every of them with 300
filtering capacitors) and 10-14 layers without autorouting ?

What in Johns post gave you the idea of 1200 ball BGAs or 10-14
PCB layers?

robert

 

[John Larkin]

And depending what you have previously done (like autorouting a class
of signals
with some impedance restrictions and accordeons generation) will
forgot or not to number the ground connections on planes. Which
omission will be kept till finishing the board...

Never seen that happen. Every connection on every board is what the
schematic says. When we screw up, it's a genuine design error or
occasionally an incorrect pinout, plainly visible on the schematic.

We don't prototype; we lay out a board, formally release it as rev A,
and have manufacturing build a couple of units to test. Most of the
time, we can sell the rev A.

Pads (2005) is as buggy as any other CAD, maybe you are lucky ?

We're using Pads PowerPCB V5, which appears to have no bugs and
doesn't crash. Software this good could make a guy stop hating
Windows. When Mentor bought PADS and started migrating users, we
dropped off the support bandwagon.

I'm wandering how you're routing 1000 components (saying you have at
least two 1200 balls BGA's on board and every of them with 300
filtering capacitors) and 10-14 layers without autorouting ?

As I mentioned, it's an 8-layer board. On this particular board, there
are two fpga's and one uP, but no bga's.

http://www.highlandtechnology.com/DSS/V470DS.html

300 capacitors?!!! We generally use 3 or 4 bypass caps per supply for
each fpga, bga or otherwise. So that's, say, 9 to 12 caps for a Xilinx
3-supply fpga. A single-supply uP deserves 2 or maybe 3.

See pic in abse.

John

 

[John Larkin]

Never seen that happen. Every connection on every board is what the
schematic says. When we screw up, it's a genuine design error or
occasionally an incorrect pinout, plainly visible on the schematic.

We don't prototype; we lay out a board, formally release it as rev A,
and have manufacturing build a couple of units to test. Most of the
time, we can sell the rev A.


We're using Pads PowerPCB V5, which appears to have no bugs and
doesn't crash. Software this good could make a guy stop hating
Windows. When Mentor bought PADS and started migrating users, we
dropped off the support bandwagon.


As I mentioned, it's an 8-layer board. On this particular board, there
are two fpga's and one uP, but no bga's.

http://www.highlandtechnology.com/DSS/V470DS.html

300 capacitors?!!! We generally use 3 or 4 bypass caps per supply for
each fpga, bga or otherwise. So that's, say, 9 to 12 caps for a Xilinx
3-supply fpga. A single-supply uP deserves 2 or maybe 3.

See pic in abse.

John

Oops, sorry, that one is 6 layers. We've recently done bga's in six,
too.

John

 

[Tom]

For just pcb, Dan has a windows installer I've pre-tested. It's
mingw-based, no cygwin required.

Hi

Don't suppose you have some kind of link to this do you?

Tried a search around the web, found several references, but all seem
to be related to something called wcalc.


Tom

 

[DJ Delorie]

Don't suppose you have some kind of link to this do you?

"Pre-tested". He sent it directly to me. If you have mingw
installed, you can build it from the pcb sources - the scripts are
included.

 

[joseph2k]

Morning All
[...]
The second question....

This is kind of related to the first, I'd be interested to know if
everyone designs their PCB's from the schematic stage upwards on
computers, or whether there are many people creating the PCB layout
only?

Tom

I've come across a number of commercial designers that still route
manually. They'll go the circuit diagram route only if the board
complexity demands it (say 20 or more packages). They say the main
reason is time saving from not having to fart about creating unique
library components and the ensuing struggle with third rate diagram
editors.

There is a company with a good product that i tried and liked a long time
ago. The company is still around and i am thinking of buying a new copy
just to see the upgrades. Yes, my old 286/386 version is still running.
Schematic capture and pwb manual / auto routing. us $995 for the current
version.

http://www.holophase.com/