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pcb fab for low power plane impedance

Discussion in 'Electronic Design' started by [email protected], Apr 8, 2007.

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  1. Guest

    Can anyone recommend a pcb fab (not necessarily in the UK) that can
    fabricate a board in which the spacing between the power and ground
    planes can be around 65um or less? The complete board has 16 layers
    and there are two power/ground layer pairs that I would like with as
    small a gap as possible. The reason is, I have only recently
    understood that the power plane impedance above the last zero of the
    decoupling caps (~ 30MHZ) is just given by the bare pcb self-
    inductance. The bare pcb self-inductance is proportional to the inter-
    plane gap and so I want this as small as possible. The pcb fab that my
    employer habitually uses can only fab boards with a gap h=150um with
    er=4.2 dielectric which corresponds to a power plane impedance of |Z|
    =130mOhms at 100MHz. However, I've heard anecdotally that some pcb
    fabs will do 65um.

  2. Guest

    It's not such a big deal. It is a patented process and you will have
    to find a shop that is ZBC approved. It's ridiculous but there you
    have it. At least that's how it works out in North America. And where
    did you get that 30MHz figure from? Are you using 0805 caps or
    something? You have to use 0201caps with two vias per pad.
    Anyways, you have to pay a fee to use this PCB technology. You can
    dance around the issue if you can convince an unlicensed PCB shop that
    you are not using the PCB as a capacitor, but to "control impedance".
  3. John  Larkin

    John Larkin Guest

    Hi, Stephen

    What are you building? At 16 layers, it must be ambitious.

    I've done a bit of TDR testing of actual PCBs, without and then with
    bypass caps. It appears to me that with moderate (say, 100-250 um)
    plane spacings, there's a generous overlap of frequency ranges in
    which the plane is a good bypass, and where the caps are effective. So
    there's no need to go to very thin dielectrics.

    And decoupling caps are still low impedance past their series
    self-resonant points. They don't become useless, they simply look like
    a cap in series with their small lead inductance, no surprise.

    So go with a reasonable plane spacing and pepper the board with 0805
    or 0603 caps; 0.1 or 0.33 uF are good choices and are cheap. There's
    really no justification for mixing cap values... the ESL is determined
    by body size and vias, so more C is better. The Spice models that
    people love to publish, with the bypass SRF dips all superimposed, are
    just plain (plane?) silly.

    Is your board impedance controlled? That gets nasty at high layer

  4. Jeff L

    Jeff L Guest

    I never understood some of those claims - I still see things like a 0.01 uf
    cap in // with a 0.1 in // with a 0.33 uF cap, sometimes even in data
    sheets!. (I suppose if someone spaced the caps apart enough, it could form a
    nasty LC Pi filter, and the different values could dampen the different
    resonances) It might be left from the days of through hole and high
    impedance electrolytics // ed with a disc cap. A smaller capacity MLCC cap
    is not as good at high frequency as a larger capacity cap in the same
    package and construction methods. Cap data sheets which show resonant points
    / impendence graphs show a shift to the left with respect to frequency in
    the self resonant points as the cap capacity shrinks, with larger caps
    showing a lower impedance then the smaller caps before, at and after the
    self resonant point. Series inductance is the limit, not the cap size

    For really good bypassing you can try the 0306, 0508 and 0612 capacitors for
    much lowered inductance! They seem to work quite well, but it's likely
    cheaper to plop down several 0603 caps in // then to buy one "sideways" low
    impedance cap. Using more then one via per pad also helps lower the
  5. vasile

    vasile Guest

    The biggest problem for manufacturer is not using the ZBC1 or ZBC2
    materials but:
    - registration problems using very low thickness material
    (any lamination need a central core with a largest thickness than the
    others layers of the lamination)
    - simetry problems in laminated stack (the laminations must be
    - keeping the number of laminations as low as possible (most
    manufacturesr will say 3)
    - blind and buried vias (including laser drilled vias) can't be
    manufactured on less than
    0.003" or 0.0025" tickness by most manufacturers

    Even the gap between power and ground is less than 65um, some vias
    connected with power or ground
    will require copper plating, which will increase the copper layer

    So, you need a deep talk with your manufacturer before sending the
    gerbers. The problem with those talks
    are the fact that often you need to redesing entire stuff once or
    twice before they gave you the ok for manufaturing.

    I will focus to tawanese manufactures if the price is an issue.
  6. Guest

    I'd like to see sources for either claim. We are in the process of
    transferring large chunks of our startup capital into the pockets of
    consultants which are making us place the classic "octave of caps"
    like 18pf, 22pf, 33pf,47pf, 100pf on sensitive analog nets. We are
    running at 6GBps+ and looking at mV of noise on reference signals.

    I understand that the superposition of bode plots for each cap is
    meaningless since the point we are decoupling doesn't "see" the caps,
    it sees what it sees. The caps are "parasitic L" further away than the
    point that needs the charge.

    My personal take on it is to reduce the parasitic L by using 0201 caps
    with two vias per pad, and use the largest C value possible in the
    package. A point of view not shared by others.
  7. John  Larkin

    John Larkin Guest

    There's no shortage of sources for claims here. There are a lot of
    silly claims.
    Not Howard Johnson, I hope! All those caps are ludicrous.
    Overkill. I do tiny signals with picosecond timing that would be
    trashed by millivolt noise, on the same board with uPs and bus
    interfaces and switching regulators. Most of our jitter problems can
    be found with a 1 MHz oscilloscope, looking at supply ripple and such.

    As I noted, the ground planes themselves are an excellent
    low-impedance structure, with a broad overlap with a scattering of
    caps. The dual-via thing doesn't help enough to matter.

    Fire those consultants before they bleed you dry, and get your product
    working. Where are you located?

  8. Guest

    Hi John,
    I need 0201 caps so I can squeeze all the decoupling, coupling and
    terminating networks close enough to the MLF16 packages. It would be a
    strange sight to see MLF16 with something as big as 0603 or 0805s
    around it. 0402 is already hampering me enough as it stands.

    The problem I think we have is that our board is so physically small,
    that we can't get any significant charge stored in PCB. The planes are
    eaten up by vias.

    I can understand using board capacitance if you're building VME sized
    cards or 19 inch rack mount stuff. My stuff is the size of a CC.

    What's wrong with Johnson? I thought he was the one backing the
    "biggest cap you can find" theory?
  9. Guest

    Thanks for hint about ZBC cores, I had not heard of this core
    material, their
    website says that a core called BC12 has er=4.2 and the gap between
    the power and ground plane is 12um.
    I wrote a little program to numerically (using R.F.Harrington's method
    moments) solve the scalar Helmholtz equation for the electric field in
    gap between the power and ground plane. I assumed that the E-field was
    in the z-direction (normal to the planes) and that it did not depend
    on z
    so it was just Ez(x,y) and that the effect of the decoupling caps
    be modelled as line sources of displacement current extending in the
    z-direction between the planes. I looked at the results of this
    program in
    order to get a feel for what is going on in terms of a circuit model
    for power
    plane impedance.

    At low frequency the impedance of a bare pcb (without any decoupling
    is the impedance the planar pcb capacitance Cpcb. At higher
    there is a zero in the impedance when the planar capacitance cancels
    bare pcb inductance Lpcb. Values for a 100mm x 100mm area with er=4.2
    the gap h=150um are Lpcb=114pH and Cpcb=2.5nF with the zero at about
    The decoupling caps are connected in parallel and attached to the
    joining Lpcb and Cpcb. The Spice network would be,

    Lpcb port n001 114pH
    Cpcb n001 0 2.5nF
    * One species of cap, 20 caps each with Lesl=1.5nH and C=100nF
    Leff n001 n002 75pH
    Ceff n002 0 2uF

    where Leff and Ceff are the effective series inductance and
    of a string of decoupling caps of a single species all in parallel.

    If there are enough decoupling caps so that the effective inductance
    of the decoupling caps is less than the pcb inductance (Leff<Lpcb) and
    Ceff>Cpcb then the zero of the decoupling caps at 1/sqrt(Leff*Ceff)
    not appear and there is a zero at 1/sqrt(Lpcb*Ceff) which is below
    resonance of the caps alone. Above this frequency the pcb looks
    That is how I got the 30MHz figure in my original post; I found that
    if I
    used many small value caps (say 1nF), the expected hole in the
    at the (relatively high frequency) resonance of the small caps did
    appear and the resonance was always at the lower frequency of
    1/sqrt(Lpcb*Ceff). For the typical values in the example, this zero is
    above 10MHz.

    Above this zero the power-plane impedance looks like the impedance
    of the bare pcb as Z=s*Lpcb. Then, there is a closely spaced pole/zero
    that marks the point at which the power plane impedance looks exactly
    a bare pcb. This pole/zero pair is at 1/sqrt(Leff*Cpcb). For the
    this is at 370MHz.

    The bare pcb inductance Lpcb is proportional to the interplane gap
    since the power plane impedance is Z=s*Lpcb above the zero at
    1/sqrt(Lpcb*Ceff), it makes sense to have a small gap as possible and
    the ZBC cores look interesting. However, the website
    says that
    the use of these cores can reduce the number of decoupling caps, but
    power-plane impedance only goes as s*Lpcb provided that there are
    decoupling caps that Leff<Lpcb. If the number of caps is reduced so
    Leff>Lpcb then the power plane impedance is dominated by the
    inductance of the caps and Z=s*Leff and you've lost the effect of the
    pcb inductance until the frequency is above the pole/zero pair at
    1/sqrt(Leff*Cpcb) at which the pcb looks exactly like a bare pcb.

  10. Guest

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