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pcb debugging

Discussion in 'PCB Layout, Design and Manufacture' started by ben123324, Jan 19, 2012.

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  1. ben123324

    ben123324

    2
    0
    Jan 19, 2012
    hey, i am working on building my next tesla coil, and i came up with this driver in eagle-cad. i usually end up missing some minor detail that bites me once i finish etching the board. can anyone compare the schematic to the board and see if i missed something? even a basic electrical rule that the board violates would be greatly appreciated(my previous design was missing power headers).

    well here they are:
    drsstcv1.0.png
    drsstcv1.0 brd.png

    thanks
    -ben
     
  2. Harald Kapp

    Harald Kapp Moderator Moderator

    9,541
    1,967
    Nov 17, 2011
    Hard to say since checking a circuit without knowledge of the requirements and the expected function is difficult. Just a few notes:

    1) You're using only 5 out of 6 gates of the 74LS14. While it is generally o.k. to leave TTL inputs open, I recommend you connect the unused input to GND or VCC via a resistor (100 Ohm - 1kOhm). This will ensure that the circuit will operate with CMOS components, too. Plus, as this circuit is intended to work in the vicinity of a Tesla coil, you can expect a lot of electromagnetic interference (EMC). Tying every node to a defined potential will help to ensure stability.

    2) The gate of Q2 is floating. This may cause trouble when nothing is connected to JP2. Add a resistor from gate to GND. The value depends on what current can be supplied at JP2. I suggest something on the order of 1kOhm - 10kOhm. Also a series resistor from JP2 to the gate of Q1 can help to protect the gate from voltage spikes on JP2.

    3) I assume you've done the ERC and DRC checks in Eagle, so in principle the layout should be o.k. I can't tell you about rule violations without knowing the rules. You should know them from your requirements (voltages, expected currrents etc.).
    One point, however, that is also related to EMC: Since you're using a double sided PCB anyway, you should take advantage of this fact and add a GND plane on the top layer (red). I'm not very familiar with Eagle, but a combination of POLYGON and RATSNEST commands can generate filled planes which you have to connect to GND. This can possibly ease the layout of the other signals on the bottom side of the PCB since now all GND connections can be made directly from the TOP layer.

    Regards,
    Harald
     
  3. ben123324

    ben123324

    2
    0
    Jan 19, 2012
    okthanks for the quick reply. i will tie the open inverter to ground, thanks for pointing that out. dont wory about emi, i have that covered(literaly). as for a ground plane, the red jumpers just represent a jumper wire, as i can only make single sided boards. q2 will alyways be hooked up, its overcurrent detection. with current feedback coil, its absolutly necisary. i think that covers everything.

    again, thanks for the quick reply, its greatly apreciated!
    -ben
     
  4. Harald Kapp

    Harald Kapp Moderator Moderator

    9,541
    1,967
    Nov 17, 2011
    Ben,
    I've noticed something else. Your decoupling capacitors are not well connected. Take e.g. C9, which has a very long trace going to Pin 7 of IC1. This long trace wil act as an inductance and drastically reduce the decoupling effect of the capacitor.
    The same goes for C7, C8.
    ICs 3 and 4 don't seem to have decoupling at all.
    Better place the Cs as near as possible to the ICs and connect them with very short traces first, then route the rest.

    Also: do you need the fat traces everywhere? If you could use smaller traces, a few of the jumper wires could be saved.

    Reagrds,
    Harald
     
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