Hard to say since checking a circuit without knowledge of the requirements and the expected function is difficult. Just a few notes:
1) You're using only 5 out of 6 gates of the 74LS14. While it is generally o.k. to leave TTL inputs open, I recommend you connect the unused input to GND or VCC via a resistor (100 Ohm - 1kOhm). This will ensure that the circuit will operate with CMOS components, too. Plus, as this circuit is intended to work in the vicinity of a Tesla coil, you can expect a lot of electromagnetic interference (EMC). Tying every node to a defined potential will help to ensure stability.
2) The gate of Q2 is floating. This may cause trouble when nothing is connected to JP2. Add a resistor from gate to GND. The value depends on what current can be supplied at JP2. I suggest something on the order of 1kOhm - 10kOhm. Also a series resistor from JP2 to the gate of Q1 can help to protect the gate from voltage spikes on JP2.
3) I assume you've done the ERC and DRC checks in Eagle, so in principle the layout should be o.k. I can't tell you about rule violations without knowing the rules. You should know them from your requirements (voltages, expected currrents etc.).
One point, however, that is also related to EMC: Since you're using a double sided PCB anyway, you should take advantage of this fact and add a GND plane on the top layer (red). I'm not very familiar with Eagle, but a combination of POLYGON and RATSNEST commands can generate filled planes which you have to connect to GND. This can possibly ease the layout of the other signals on the bottom side of the PCB since now all GND connections can be made directly from the TOP layer.
Regards,
Harald