PCB Arcing/spark gap

[Bob Stephens]

A while back there was a discussion here about the minimum inter - trace
distance to prevent unintentional spark gaps on PCB's. Anyone know of a
table or a rule of thumb for spacing vs. applied voltage for inner layers?
I've googled a fair amount and haven't really come up with anything.

TIA


Bob

 

[Active8]

A while back there was a discussion here about the minimum inter - trace
distance to prevent unintentional spark gaps on PCB's. Anyone know of a
table or a rule of thumb for spacing vs. applied voltage for inner layers?
I've googled a fair amount and haven't really come up with anything.

TIA

Bob

We probably included links in that recent thread. You know, when you
go to google, if you click on the "groups" link and find this
group's archive, you can then select to search within this group
only. When I'm looking for a past thread, I'll search on the names
of the posters that I remember participating, the year, and as much
of the subject line as I can remember. Text in the body of the posts
can also be helpful. Ferinstance, I kinda remember someone posting a
link to an article that covered "crosstalk" between the traces, so I
might use that keyword, also.

 

[Bob Stephens]

We probably included links in that recent thread. You know, when you
go to google, if you click on the "groups" link and find this
group's archive, you can then select to search within this group
only. When I'm looking for a past thread, I'll search on the names
of the posters that I remember participating, the year, and as much
of the subject line as I can remember. Text in the body of the posts
can also be helpful. Ferinstance, I kinda remember someone posting a
link to an article that covered "crosstalk" between the traces, so I
might use that keyword, also.

Thanks Mike. I wasn't aware of that feature in Google.

Bob

 

[Jim Meyer]

A while back there was a discussion here about the minimum inter - trace
distance to prevent unintentional spark gaps on PCB's. Anyone know of a
table or a rule of thumb for spacing vs. applied voltage for inner layers?
I've googled a fair amount and haven't really come up with anything.

TIA
Bob

Breakdown voltages for PC boards are highly process dependant.
Your question can only be answered by a particular board manufacturer
for one particular type of board.

Jim

 

[James Meyer]

.....and thereafter depends on the type/amount of crude deposited on the
board during assembly/testing/shipping/installation/operation of
product.....

Terry

Note the "inner layers" part of the original post. That spec should be
completely under control of the board manufacturer and not affected (much) by
subsequent processing of the board.

Jim

 

[Terry Given]

Breakdown voltages for PC boards are highly process dependant.
Your question can only be answered by a particular board manufacturer
for one particular type of board.

Jim

......and thereafter depends on the type/amount of crude deposited on the
board during assembly/testing/shipping/installation/operation of
product.....

Terry

 

[Terry Given]

Note the "inner layers" part of the original post. That spec should be
completely under control of the board manufacturer and not affected (much) by
subsequent processing of the board.

Jim

oops, didnt see that - you are quite right, the aforementioned crud issues
are irrelevant - assuming the inner layer traces come out (eg via/pad)
sufficiently far from each other.

I have however looked into this issue in particular, when looking at
designing planar smps transformers to run from 1kVdc. I never got a
satisfactory answer from the pcb manufacturers. IIRC Coombs' printed
circuits handbook gives you an idea of the dielectric strength of the
laminate itself, but the real issue is the dielectric strength of, and the
presence of voids in, the resin (b-stage prepreg IIRR). Making sure there
are no voids is the hard bit.

Terry

 

[James Meyer]

oops, didnt see that - you are quite right, the aforementioned crud issues
are irrelevant - assuming the inner layer traces come out (eg via/pad)
sufficiently far from each other.

I have however looked into this issue in particular, when looking at
designing planar smps transformers to run from 1kVdc. I never got a
satisfactory answer from the pcb manufacturers. IIRC Coombs' printed
circuits handbook gives you an idea of the dielectric strength of the
laminate itself, but the real issue is the dielectric strength of, and the
presence of voids in, the resin (b-stage prepreg IIRR). Making sure there
are no voids is the hard bit.

Terry

If high voltage is a sufficient issue, the board manufacturer can test
the breakdown voltage per board and only ship boards that pass the test. Of
course, you will have to pay a premium for that sort of testing.

Jim

 

[Terry Given]

If high voltage is a sufficient issue, the board manufacturer can test
the breakdown voltage per board and only ship boards that pass the test. Of
course, you will have to pay a premium for that sort of testing.

Jim

individual testing was the only solution I could find, too. In the end I
didnt use a planar for that app - the total cost was too high, mostly due to
the type of switch I could use (1700V) restricting frequency, thereby fixing
Np,Nz at high values, which makes it difficult in planar.

cheers
Terry