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parallel fets

Discussion in 'Electronic Design' started by Jamie Morken, Feb 29, 2008.

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  1. Jamie Morken

    Jamie Morken Guest


    I was thinking about how to minimize switching losses and also on state
    resistance, as well as having reduced gate driver requirements, and
    was thinking this would be a good idea:

    use 1 fet with very fast rise/fall times as well as low gate charge
    (but high on-state resistance)

    then the rest of the parallel fets rise/fall times as well as gate
    drive requirements are almost irrelevant. As long as they switch
    within say 100ns they will relieve the single fet which hopefully
    fully switched within 10ns, and then had normal Rds(on) losses
    for 90ns. Then for 100kHz switching, the other lower Rds(on) fets
    would take all the load for 10us, while the other "pulse" fet has
    a chance to cool down until the next 100ns switch point.

    So the benefits are reduced gate drive current requirements,
    and not having to find fets that have BOTH low Rds(on) as well
    as low gate charge and fast rise/fall times.

    Another idea I was thinking, to use a zero ohm resistor on the
    single fast fet, as the gate ringing may not matter on that
    fet as long as it is able to stay turned on for at least 100ns
    before the ringing turns it off.

    Would these ideas be practical?

  2. legg

    legg Guest

    It's called 'assisted switching'. Your version would transfer all
    switching losses to the faster part. Switching losses can be a
    significant portion of the total, in a switching element. Gate drive
    loss due to CRSS in the the slower elements can be reduced, if a
    suitable path for the current is provided.

    Most assisted switching circuits attempt to reduce losses dissipated
    in the main switches by storing/recovering the energy involved. If
    this can be done without producing extreme dv/dt or di/dt, so much the

  3. D from BC

    D from BC Guest

    Warning: I'm a newbie in this area...

    The idea sounds ok.
    One mosfet acts like a sword and another mosfet finishes of the
    switching like a sledge hammer.

    For mismatched parallel mosfets (single wimpy mos driver), the mosfet
    with the heaviest gate capacitance may rule. Other parallel Mosfets
    with lighter gate capacitances follow the retarded rate of the driver.
    Assuming Cg1>>Cg2. Fixable I guess with multiple drivers.

    I've seen some articles where power mosfets and bipolars are combined
    in parallel in an effort to reduce heat.

    D from BC
    British Columbia
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