output resistance of ota

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What is the large signal output resistance of this circuit?
http://users.ece.gatech.edu/phasler/Courses/ECE4430/projects/project4/ota.jpg
If i put V+ and V- to groud, a test voltage generator Vx at the
output, the current Ix is divided between RdsM4 and RdsM2+RdsM5... The
current in RdsM4 is (Vdd-Vx)/RdsM4 (i consider Vdd because i'm
interested in large signal output voltage), the current in RdsM2+RdsM5
is Vx/(RdsM2+RdsM5)..is this right?
Thanks in advance

 

[Kevin Aylward]

What is the large signal output resistance of this circuit?
http://users.ece.gatech.edu/phasler/Courses/ECE4430/projects/project4/ota.jpg
If i put V+ and V- to groud, a test voltage generator Vx at the
output, the current Ix is divided between RdsM4 and RdsM2+RdsM5... The
current in RdsM4 is (Vdd-Vx)/RdsM4 (i consider Vdd because i'm
interested in large signal output voltage), the current in RdsM2+RdsM5
is Vx/(RdsM2+RdsM5)..is this right?
Thanks in advance

Assuming no clipping, the "large (vllotage) signal" output resistance could
well be the same as the "small signal" output resistance. It depends on the
load. Typically this type of circuit is driven into a buffer to, e.g. to
keep the gain high, in which case, the current in the transisters don't
change much. Usually one speciically designs ths stage such that that is
what happens. So...

ro = Va/Id, of each transister.

Where Va is the "Early voltage". If Id is only varied a small amount, ro
remains approximately constant.

Now, knowing that ro of m4 and ro of m2 are in parallel, and the expression
for ro, you should be now able to calcualte the instantaenous Ro at Vx, as
the current is M2 and M2 varied.

Kevin Aylward

www.anasoft.co.uk
SuperSpice

 

[[email protected]]

Thanks for the answer...

Now, knowing that ro of m4 and ro of m2 are in parallel, and the expression
for ro, you should be now able to calcualte the instantaenous Ro at Vx, as
the current is M2 and M2 varied.

Why are m4 and m2 in parallel? In large signal analysis i should
consider also Vdd (in small signal analysis instead Vdd is signal-
ground, so m4 and m2 are in parallel)... or not?

 

[Kevin Aylward]

Thanks for the answer...

Why are m4 and m2 in parallel?

er...well approximatly. Technically m2 source connects through the 1/gm of
m1 to ground

In large signal analysis i should
consider also Vdd (in small signal analysis instead Vdd is signal-
ground, so m4 and m2 are in parallel)... or not?

Only changes need to be considered. Vdd don't change. Technically there is a
"DC resistance" of (Vdd- Vdrain)/ID, but this doesn't really have much
relevance to calculating the "large signal" gain. As I noted, even if Vx
changes a few volts, ro is still the same as its small signal value for
light loads. If you take a lot of current such that this is no longer true,
the stage wont work well, or at all. A lowish resistive load will kill the
gain. Tyically, this stage drives a pmos.

Kevin Aylward

www.anasoft.co.uk
SuperSpice

 

[[email protected]]

Thanks for the answer....
I think i have understand now.....if i consider large signal analysis,
all voltage and current sources that don't vary in time (as
Vdd,Vss,ecc) are ground signal (for voltage sourcer) or open circuit
(for current bias sources), is it right?