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Orcad Layout Footprints

Discussion in 'CAD' started by Stefan, Feb 25, 2004.

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  1. Stefan

    Stefan Guest

    I need OrCad Layout Plus footprints for chip package CSP1616/277 and
    SAMTEC Edge Connector 120-pin QTE-060-01-L-D-EM2-GP. May be I have
    them in a library but don't know. How can I find them. Also if I have
    to make them how to pick the righ padstacks.

    Any help will be greatly appreciated.

    Stefan
     
  2. qrk

    qrk Guest

    You can make your own footprints quite easily for non-BGA parts.

    Samtec usually has suggested footprint information on their web site.
    The device you mention has a nice PDF of the footprint. This is a
    relatively easy footprint to make yourself. I doubt you'll find this
    in an Orcad library.

    I assume your other package is a chip-scale BGA. Check manufacturer's
    web site for suggested footprint information. Xilinx and Motorola have
    good info on BGA footprints. You may find something in the Orcad
    library that you can modify. Open the library editor and search
    through the relevant footprint libraries. You might want to start with
    the "BGA" library. If you need to generate a new footprint with via
    fanout, I have left a basic program to generate BGA footprints at
    http://www.pcbstandards.com/forums/showthread.php?s=5cd4b03ee275826bcbddf24ab24e3c10&threadid=203
    Look at the end of the thread, author: qrk. You can generate a 1000+
    pin BGA footprint in a couple minutes + more time to add the graphics.
    0.8mm pitch BGAs are not much fun to wire up. :(

    Mark
     
  3. Stefan

    Stefan Guest

    Mark, thank you for the information. Actualy the footprint I am
    looking for is for RICOH chip R5C554 and it is not BGA. The manual
    says that the chip comes in
    BGA272pins or CSP1616/277-pin pacage. I assume that CSP is chip scale
    package PGA? I do not have the chip yet.

    Any suggestions?

    Stefan
     
  4. qrk

    qrk Guest

    According to the Ricoh data sheet, the CS is a chip-scale package
    which is a BGA with 0.8mm pitch grid array. This is an unpleasant
    device to wire up due to the pitch. Pray that the inner pins are
    mostly power and ground. Fortunately, they have large clear areas
    which will make things a bit easier for you.

    Check out the Xilinx link below. Starting at page 17, look for
    dimensions on the CS144 package on page 19. This will get you started
    in the right direction.
    http://direct.xilinx.com/bvdocs/userguides/ug112_Device_Packaging.pdf
    This document also has good info on the different packaging types and
    how they're built.

    If you can handle the size, the BGA part is much easier to wire up due
    to the 50 mil pitch.

    Either way, you normally make a via fanout to route the inner
    connections. The program I mentioned will do this quite painlessly -
    unless your adverse to wanker basic. After creating the part, delete
    the unneeded pins.

    Mark
     
  5. Stefan

    Stefan Guest

    Thanks again,
    I also have another problem. This one will be very easy for you.
    I have headers on the board. How to make sure that the pin will fit in
    the finished hole. I see the size of the pad in the padstack dialog
    box, but can not understand how to find the size of the openning.

    Stefan
     
  6. |> Thanks again,
    |> I also have another problem. This one will be very easy for you.
    |> I have headers on the board. How to make sure that the pin will fit in
    |> the finished hole. I see the size of the pad in the padstack dialog
    |> box, but can not understand how to find the size of the openning.

    The hole size in the padstack entry named "drill". Clear enough? I
    think you have to check with your board house to see if they interpret
    this as the actual drill size to use for the raw hole, or the target
    finished hole size after plating. For most holes you want this big
    enough that the difference will not matter.

    --
    NOTE: to reply, remove all punctuation from email name field

    Ned Forrester 508-289-2226
    Applied Ocean Physics and Engineering Dept.
    Oceanographic Systems Lab http://adcp.whoi.edu/
    Woods Hole Oceanographic Institution, Woods Hole, MA 02543, USA
     
  7. qrk

    qrk Guest

    On 4 Mar 2004 07:14:01 -0800, (Stefan) wrote:

    [snippage]
    Look at the "Padstacks" spreadsheet (Shift-T). There are two entries,
    DRLDWG and DRILL. The drill diameters should be the same in these two
    lines. DRLDWG shows symbols for each drill hole size and type (plated
    or unplated). DRILL graphically shows the diameter of the drill hole
    so you can check for problems like breakout. Be sure to specify to the
    board house that your drill diameters are "finished size". You can
    modify the padstack parameters whilst in your design.

    BTW, if there are lots of padstacks in the spreadsheet, use the pin
    tool (button with a "1" in a circle) to highlight the pin, then do the
    Shift-T thingy. The desired padstack will be selected in the
    spreadsheet.

    If your using the Orcad canned libraries and need to modify them, copy
    the part to your own library and modify. Be sure to use a different
    footprint name. All my custom footprints end with ".PRT". This
    eliminates confusion between Orcad libraries and mine.

    Mark
     
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