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OPAMP simulation and PROTEL

Discussion in 'Electronic Design' started by Edgar Y. Lobachevskiy, Apr 27, 2004.

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  1. Hi all:

    I am running a simulation on basic integrator using PROTEL. when I
    have a bleeding resistor and capacitor in parallel in the feedback I
    get expected results. But when I add one more resistor in series
    with the above components (that are in parallel themselves), the
    output voltage increases by factor of 1000. I did the math and
    solved the problem analytically and it does not support such an
    increase in Vout.

    Did anybody have such problems? Or does anybody have an idea why
    this may happen? I would appreciate any advise.

    I already tried changing time step interval.

    Thank you,

    edgar
    univ hawaii
    usa
     
  2. What do you mean that it "increases by a factor of 1000"? The initial
    voltage or the slope? What's the initial voltage across the capacitor?
    What are the component values?

    Best regards,
    Spehro Pefhany
     
  3. Better still, how about a schematic (in
    alt.binaries.schematics.electronic or on a web page, or in ASCII.)
     
  4. When I said 'increases by factor 1000' I meant that if the voltage without
    the series resistor was 50mV, then with the addition of 100K resistor in
    series, Vout jumps to 50V. My analytical derivation does not support 50V at
    Vout. I submitted another post with the circuit of the opamp in
    alt.binaries.schematics.electronics under OPAMP SIMULATION AND PROTEL
    subject. Please let me know what you think of the discrepancy and if it can
    be verified.

    edgar
    unv hawaii
    usa



    http://www.speff.com
     
  5. tk

    tk Guest

    What version of Protel? Why not ask on the Protel group??
     
  6. Thanks for the emailed schematic. (BTW, your 180KB JPG file can be
    reduced to about 7KB if changed to a b/w, cropped GIF.) I gather you
    simultaneously posted this to alt.binaries.schematics.electronic, but
    I don't see it here.

    Anyway, I don't think the schematic and subsequent output waveforms
    you sent really make your problem any clearer. And there appear to be
    inconsistencies between those and your original description. Pending
    discussion here (or in alt.binaries.schematics.electronic), I've
    emailed a reply.
     
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