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Op-Amp based control-loop, help with simulation

Discussion in 'Electronic Design' started by ROb, Oct 22, 2007.

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  1. ROb

    ROb Guest


    I am trying to build a simple control-loop to build a current-source.
    Control-loop will be controlling a buck SMPS, Fs=300 kHz. Control-loop
    is Type I.

    I'm using single-supply op-amp, Vref attached to "+" node of amp,
    feedback through 80k ohm resistor to "-" input. A 0.1 uF cap is attached
    from "-" to op-amp output. 0 dB open-loop gain with above = ~20 Hz.

    I can't seem to get the PSPICE / Micro-cap step-response to match
    Matlab's closed-loop step response. Matlab shows 125/s step-response
    settles with-in 45 ms (very acceptable), SPICE shows the system settles
    with-in 10 us!

    I simulate closed-loop by having op-amp output drive a 10 uH / 47 uF L/C
    filter, output of filter goes to input side of 80k resistor. I apply a
    step to Vref at 100 ns to go from 0 to 1V. Output of op-amp responds
    with ~10-15 us delay to step with nearly 0 overshoot.

    I would expect in "closed-loop" my op-amp output would reach 1V output
    in ~50 ms. Oddly my AC simulation of my op-amp circuit matches Matlab's
    open-loop gain, open-loop crosses 0 dB @ 20 Hz, with DC gain of ~42 dB.
    I can change the .1 uF cap to 100 uF and the SPICE step-response is the

    What is a "failsafe" way of simulating my closed-loop op-amp operation?
    I'm taking the SMPS out of the picture even, just limiting it to the op-
    amp alone.

  2. Guest

  3. J.A. Legris

    J.A. Legris Guest

    Step 1. Post both your schematics and/or netlists somewhere.
    Step 2. Post a link here.
    Step 3. Solution magically appears in a few hours.
  4. D from BC

    D from BC Guest

    Step 4. Mail check. :)

    D from BC
  5. Marra

    Marra Guest

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