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on which edge does a FF trigger

  • Thread starter Wouter van Ooijen
  • Start date
W

Wouter van Ooijen

Jan 1, 1970
0
I am confused about the edge on which a FF triggers. My intuition
would say that any logic symbol with a plain wedgie (no inverting
blob) should trigger on the positive edge, but maybe that's too
simple.

H&H 2nd edition P508/509 states that a JK triggers on the negative
edge, and an edge-triggered FF on the positive edge. But it is not
clear whether that refers to the implementation as shown, or to thje
bare logic symbol. Most JK symbols do have the inverting blob on the
clock input.

P510 suggests that both dividers behave the same, which would imply
that the plain JK symbol triggers on the negative edge,

Yet P511 states that the shown ripple divider clocks on the negative
edge, the JK symbols do have the inverting blob, so the plain JK
symbol would clock on the positive edge.

My tenative conclusion is that a plain (no inverting blob) D FF clocks
on the positive edge. But on which edge clocks a plain JK FF?
Positive, neative, or worse: there is no standard?

Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
PICmicro chips, programmers, consulting
 
C

colin

Jan 1, 1970
0
Wouter van Ooijen (www.voti.nl) said:
I am confused about the edge on which a FF triggers. My intuition
would say that any logic symbol with a plain wedgie (no inverting
blob) should trigger on the positive edge, but maybe that's too
simple.

H&H 2nd edition P508/509 states that a JK triggers on the negative
edge, and an edge-triggered FF on the positive edge. But it is not
clear whether that refers to the implementation as shown, or to thje
bare logic symbol. Most JK symbols do have the inverting blob on the
clock input.

P510 suggests that both dividers behave the same, which would imply
that the plain JK symbol triggers on the negative edge,

Yet P511 states that the shown ripple divider clocks on the negative
edge, the JK symbols do have the inverting blob, so the plain JK
symbol would clock on the positive edge.

My tenative conclusion is that a plain (no inverting blob) D FF clocks
on the positive edge. But on which edge clocks a plain JK FF?
Positive, neative, or worse: there is no standard?

heres my 2 pence worth

positve logic = positive edge
negative logic = negative edge ie with blobs or wedges
dont care logic = could be any edge .. who knows ??

master-slave jk fip flops latch the jk state on one edge then transfer it to
the output on the next edge, maybe that cuases more confusion?

Colin =^.^=
 
W

Wouter van Ooijen

Jan 1, 1970
0
master-slave jk fip flops latch the jk state on one edge then transfer it to
the output on the next edge, maybe that cuases more confusion?

That is what a fellow teacher told me, but from my memory (and from
the implementation shown in HH p508) this is not true: a MS-JK latches
the input state on one *level* of the clock, and transfers it to the
output on the other level. The total effect is sample-and-transfer on
the edge.


Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
Webshop for PICs and other electronics
http://www.voti.nl/hvu
Teacher electronics and informatics
 
P

Paul Burke

Jan 1, 1970
0
Wouter said:
I am confused about the edge on which a FF triggers. My intuition
would say that any logic symbol with a plain wedgie (no inverting
blob) should trigger on the positive edge, but maybe that's too
simple.

Not everyone uses "intentional" logic symbols- a lot of people leave the
wedgies out on circuit diagrams, and don't necessarily add circles to
active-low inputs or mark the name with a negation. the 74x73 triggers
on falling edge, the x74 on the rising edge, but without going through
the books I can't remember whether that's true for all other Ds, JKs
etc. I suppose it's up to the chip designer and what they think people want.
My tenative conclusion is that a plain (no inverting blob) D FF clocks
on the positive edge. But on which edge clocks a plain JK FF?
Positive, neative, or worse: there is no standard?

Sadly, there's no alternative to reading the data sheet for each type.

Paul Burke
 
W

Wouter van Ooijen

Jan 1, 1970
0
Not everyone uses "intentional" logic symbols- a lot of people leave the
wedgies out on circuit diagrams, and don't necessarily add circles to
active-low inputs or mark the name with a negation. the 74x73 triggers
on falling edge, the x74 on the rising edge, but without going through
the books I can't remember whether that's true for all other Ds, JKs
etc.

I checked two datasheets:

http://www.sfu.ca/phys/430/datasheets/74LS74.pdf
http://people.na.infn.it/~aloisio/sn7473.pdf

Both seem to adhere to the convention that a wedgie alone is
triggering on a positive edge, a blob (or half-arrow) inverts this.
I suppose it's up to the chip designer and what they think people want.

My question was about the symbol, not about chips. The chip designer
can of course choose what he wants (7473 and 7473A choose
differently!), I am interested in how it should be drawn as a symbol.






Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
Webshop for PICs and other electronics
http://www.voti.nl/hvu
Teacher electronics and informatics
 
C

colin

Jan 1, 1970
0
Wouter van Ooijen (www.voti.nl) said:
That is what a fellow teacher told me, but from my memory (and from
the implementation shown in HH p508) this is not true: a MS-JK latches
the input state on one *level* of the clock, and transfers it to the
output on the other level. The total effect is sample-and-transfer on
the edge.

Yes thats a more corect way of describing it, been a while since i looked at
one in detail. All the new symbols actualy leave out the inner workings
these days i had to just look at an old 1980 TTL data book to see an
internal schematic to check.

Colin =^.^=
 
T

Tam/WB2TT

Jan 1, 1970
0
Wouter van Ooijen (www.voti.nl) said:
I checked two datasheets:

http://www.sfu.ca/phys/430/datasheets/74LS74.pdf
http://people.na.infn.it/~aloisio/sn7473.pdf

Both seem to adhere to the convention that a wedgie alone is
triggering on a positive edge, a blob (or half-arrow) inverts this.


My question was about the symbol, not about chips. The chip designer
can of course choose what he wants (7473 and 7473A choose
differently!), I am interested in how it should be drawn as a symbol.






Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
Webshop for PICs and other electronics
http://www.voti.nl/hvu
Teacher electronics and informatics

It also depends on what you call the input. Say you have a negative edge
triggered FF. If it is called the "TEE" input you would have to show an
inverting blob; if it is called the "TEEBAR" input, there is no inverting
blob. The second of these does not appear to be used much. Also, the symbol
for edge triggered inputs really is supposed to show the little wedge symbol
inside the box, but not all manufacturers do that.

Tam
 
T

Tim Shoppa

Jan 1, 1970
0
Positive, neative, or worse: there is no standard?

The wonderful thing about standards is that there are so many to choose from!

For "real chips", it depends on the logic family. 74xxx families
tend to trigger on the negative edge or level, for noise immunity
reasons. CD40xx stuff tends to trigger on the positive edge or level.
There are many exceptions (not to mention the newish part numbers like
74HC4013 which mix both part numbers together!). Maybe more exceptions
than agreements... the most popular TTL D-flip-flops work on positive
levels/edges.

The "bare part" is a hopeless quest because the real bare parts are
transistors and resistors and diodes, not "flip-flops".

You really need the truth table/state table for the flip-flop in question.

Tim.
 
W

Wouter van Ooijen

Jan 1, 1970
0
For "real chips", it depends on the logic family. 74xxx families
tend to trigger on the negative edge or level, for noise immunity
reasons. CD40xx stuff tends to trigger on the positive edge or level.
There are many exceptions (not to mention the newish part numbers like
74HC4013 which mix both part numbers together!). Maybe more exceptions
than agreements... the most popular TTL D-flip-flops work on positive
levels/edges.

The "bare part" is a hopeless quest because the real bare parts are
transistors and resistors and diodes, not "flip-flops".

You really need the truth table/state table for the flip-flop in question.

I think you misunderstand my question. I want to know the
interpretation of the symbol. A square with a wedgie in it, with a
line going into the wedgie. Is that supposed to denote a
positive-edge-triggered thingie or a negative-edge-triggered thingie?
Or does the answer depend on the kind of thingie, D or JK FF? Or dies
it also depend on old-style versus IEEE symbol?



Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
Webshop for PICs and other electronics
http://www.voti.nl/hvu
Teacher electronics and informatics
 
A

Andrew Holme

Jan 1, 1970
0
I am confused about the edge on which a FF triggers. My intuition
would say that any logic symbol with a plain wedgie (no inverting
blob) should trigger on the positive edge, but maybe that's too
simple.

H&H 2nd edition P508/509 states that a JK triggers on the negative
edge, and an edge-triggered FF on the positive edge. But it is not
clear whether that refers to the implementation as shown, or to thje
bare logic symbol. Most JK symbols do have the inverting blob on the
clock input.

P510 suggests that both dividers behave the same, which would imply
that the plain JK symbol triggers on the negative edge,

Yet P511 states that the shown ripple divider clocks on the negative
edge, the JK symbols do have the inverting blob, so the plain JK
symbol would clock on the positive edge.

My tenative conclusion is that a plain (no inverting blob) D FF clocks
on the positive edge. But on which edge clocks a plain JK FF?
Positive, neative, or worse: there is no standard?

Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
PICmicro chips, programmers, consulting

The bare logic symbol clocks on the rising edge but most of the
devices you can actually buy have blobs and therefore clock on the
falling edge. There are 8 different JK flip flops in my (very old)
LSTTL data book. 7/8 have blobs. Only the 74LS109 JK FF is positive
edge triggered.

Buy a TTL data book. They make great bedtime reading!
 
R

Rich Grise

Jan 1, 1970
0
I think you misunderstand my question. I want to know the
interpretation of the symbol. A square with a wedgie in it, with a
line going into the wedgie. Is that supposed to denote a
positive-edge-triggered thingie or a negative-edge-triggered thingie?
Or does the answer depend on the kind of thingie, D or JK FF? Or dies
it also depend on old-style versus IEEE symbol?
With symbols, the standards are even worse. All you can do is have the
data sheet memorized, or on hand.

Generally, dot means "active low" and no dot means "active high", so
my first guess would be no dot + wedge => high-going edge trigger, and
so on.

Have Fun!
Rich
 
J

John Fields

Jan 1, 1970
0
My question was about the symbol, not about chips. The chip designer
can of course choose what he wants (7473 and 7473A choose
differently!), I am interested in how it should be drawn as a symbol.
 
W

Wouter van Ooijen

Jan 1, 1970
0
Buy a TTL data book. They make great bedtime reading!

I am still reading the various PIC datasheets. When I am finished with
those there is still AVR, COP8, PSoC, .... :)



Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
Webshop for PICs and other electronics
http://www.voti.nl/hvu
Teacher electronics and informatics
 
J

Jamie

Jan 1, 1970
0
Wouter said:
I am confused about the edge on which a FF triggers. My intuition
would say that any logic symbol with a plain wedgie (no inverting
blob) should trigger on the positive edge, but maybe that's too
simple.

H&H 2nd edition P508/509 states that a JK triggers on the negative
edge, and an edge-triggered FF on the positive edge. But it is not
clear whether that refers to the implementation as shown, or to thje
bare logic symbol. Most JK symbols do have the inverting blob on the
clock input.

P510 suggests that both dividers behave the same, which would imply
that the plain JK symbol triggers on the negative edge,

Yet P511 states that the shown ripple divider clocks on the negative
edge, the JK symbols do have the inverting blob, so the plain JK
symbol would clock on the positive edge.

My tenative conclusion is that a plain (no inverting blob) D FF clocks
on the positive edge. But on which edge clocks a plain JK FF?
Positive, neative, or worse: there is no standard?

Wouter van Ooijen

-- ------------------------------------
I think you maybe referring to a Master Slave JK FF.
the JK states are retained at the start of the Transition
and then used at the end of the transition of the clock and
thus sets the output then.
so this means in this case the output actually changes state
at the end of the "Said" state but using the values of the J&K at the
start !
where as the other type of JK simply uses the JK state at the start
of the transition.

I have an electronics quick text guide in PDF that covers this
area among others if you wish to see it.
it is very good and clear on explaining these things.
 
P

Paul Burke

Jan 1, 1970
0
Wouter said:
I think you misunderstand my question. I want to know the
interpretation of the symbol. A square with a wedgie in it, with a
line going into the wedgie. Is that supposed to denote a
positive-edge-triggered thingie or a negative-edge-triggered thingie?
Or does the answer depend on the kind of thingie, D or JK FF? Or dies
it also depend on old-style versus IEEE symbol?

I don't think we did. The answer is, yes, if the wedge has a circle,
things probably happen at the falling edge. But if it hasn't got a
circle, things may still happen at the falling edge- not as far as I
recall seeing in a datasheet, but certainly in schematics of circuits.
The designer hasn't bothered, or has forgotten, to put the circle in.

IEEE symbols, which were an attempt to sort all this out, never really
took off, at least in the circles I move in. Designed around the
computer and plotter capabilities of the 70s, and profoundly anti-
intuitive, they make most symbols look like a Dalek with a tram
pantograph, and the decoding of the ciphers within is a study in itself.
And in any case, circuit components rapidly got beyond the kind of thing
they can describe.

Paul Burke
 
B

Bob Stephens

Jan 1, 1970
0
IEEE symbols, which were an attempt to sort all this out, never really
took off,

Thank God!
Designed around the
computer and plotter capabilities of the 70s, and profoundly anti-
intuitive,

Hear Hear!

Bob
 
M

mike

Jan 1, 1970
0
Wouter said:
I think you misunderstand my question. I want to know the
interpretation of the symbol. A square with a wedgie in it, with a
line going into the wedgie. Is that supposed to denote a
positive-edge-triggered thingie or a negative-edge-triggered thingie?
Or does the answer depend on the kind of thingie, D or JK FF? Or dies
it also depend on old-style versus IEEE symbol?



Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
Webshop for PICs and other electronics
http://www.voti.nl/hvu
Teacher electronics and informatics

It's interesting to debate the standards. But in the end, the only way
to know for sure is to look up the vendor data on each specific part.
The fact that the part symbol fits the standard 99.99% of the time is
small consolation when your circuit doesn't work.
mike

--
Return address is VALID.
Wanted, 12.1" LCD for Gateway Solo 5300. Samsung LT121SU-121
Wanted GPIB Card for PC.
Bunch of stuff For Sale and Wanted at the link below.
http://www.geocities.com/SiliconValley/Monitor/4710/
 
W

Winfield Hill

Jan 1, 1970
0
Wouter van Ooijen (www.voti.nl wrote...
I think you misunderstand my question. I want to know the
interpretation of the symbol. A square with a wedgie in it, with a
line going into the wedgie. Is that supposed to denote a
positive-edge-triggered thingie or a negative-edge-triggered thingie?
Or does the answer depend on the kind of thingie, D or JK FF? Or dies

It's positive-edge triggering.

.. positive negative
.. ___ ___
.. | | | |
.. ---|> | ---o|> |
.. |___| |___|
..
 
W

Wouter van Ooijen

Jan 1, 1970
0
- Win

Now that is an answer from a source that I trust :)

On to the next question, which is less well-defined I am afraid. The
term master-slave flip flop, should this describe

1. Two flip-flops, which (in my idea) are edge-triggered (level
triggered would be a latch), so the total thing would be edge
triggered with a delayed output, or

2. Two latches, so the total thing is an edge-triggered FF.

To summarize: is a MS-FF one FF, or two FFs?


Wouter van Ooijen

-- ------------------------------------
http://www.voti.nl
Webshop for PICs and other electronics
http://www.voti.nl/hvu
Teacher electronics and informatics
 
R

Rich Grise

Jan 1, 1970
0
Now that is an answer from a source that I trust :)

On to the next question, which is less well-defined I am afraid. The
term master-slave flip flop, should this describe

1. Two flip-flops, which (in my idea) are edge-triggered (level
triggered would be a latch), so the total thing would be edge
triggered with a delayed output, or

2. Two latches, so the total thing is an edge-triggered FF.

To summarize: is a MS-FF one FF, or two FFs?
It's two flip-flops, which is where the master/slave bit comes
in. I've never understood that level-trigger stuff, being a black-box
seat-of-the-pants kind of guy, I figure if the output changes when
the level changes, well, it's an edge when the level changes, so
what's the diff?, but I think it has something to do with re-syncing
stuff - with an edge-trigger, you clean up all the prop delays of
previous level-triggered stuff, or something like that. From my POV,
your description of the difference between edge- and level-triggering
is as good as, or better than mine.

HTH!
Rich
 
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