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obtaining intermediate frequency with 74HC74

Discussion in 'General Electronics Discussion' started by Dee, Mar 7, 2014.

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  1. Dee

    Dee

    5
    0
    Mar 7, 2014
    Hello. First off I'm new here so hello and thanks for having me on your forum. :D

    I have a problem that's been bugging me the past days and i cannot seem to wrap my head around it.

    I know that when applying two signals to the D and CLK inputs of a 74HC74, one gets the intermediate frequency at the output Q. I have even used this in different setups and it worked well. Everything was fine with that until i asked myself why... and now for the embarrassing part...
    I know the basics of a clocked rising edge D-type flip flop but no matter how i turn and twist it i cannot explain obtaining the difference between two signals.
    So I have looked at the 74HC74 datasheet and the logic diagram but can not seem to reach a satisfying conclusion. Tried looking it up on the internet but at this point i am not even sure i know what to look for. It makes sense that there is a logic gate subtraction setup in there but i just cannot see it.
    If anyone out there brighter than me could explain this i would be very grateful
     
  2. BobK

    BobK

    7,682
    1,686
    Jan 5, 2010
    Draw out a timing diagram with the CLK and D signals and then compute the Q output from that. That might give you a sense of what is going on.

    Bob
     
  3. Dee

    Dee

    5
    0
    Mar 7, 2014
    Thanks for your replies.
    I realized the construction must be of the master-slave type but here i got stuck.
    Drawing out diagrams repeatedly was the first thing that crossed my mind. However i might as well assume my brain is defective so i ran a computer simulation using the "Logical Circuit" software. It is the best one i know for the purpose (any suggestions if anyone has a better tip is appreciated). The results did not differ to my disappointment. I ran a master-slave D type schematic. Used a clock as a constant signal source and a push button to generate random signals. I attach an image of the simulated oscillogram. Is it just me? I just cannot see it... the output doesn't look like a difference.... not like logical subtraction not like any subtraction i could possibly invent to fit the model.....
    Also tried running the 74HC74 schematic from the datasheet (using gate equivalence to compensate for the gate types missing from the software but that could not possibly be an issue) but whenever i try to run the simulation i simply get the error "oscillation"
    I do realize the answer will probably be something embarrassingly simple i keep not seeing but at thins point it is driving me nuts....
    and still inputting two sine waves yields the frequency difference.... is there something i am not considering regarding sine waves?
    Thanks for your time
     

    Attached Files:

    Last edited: Mar 10, 2014
  4. mursal

    mursal

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    Dec 13, 2013
    you waveforms look correct, to me

    As you know, a D type flip flop places the data that is applied to the D input, onto the output Q on the negative edge of the clock signal. Sometimes called a latch, because you can now remove the input signal (0V or 5V) and the output will not change. So its latched onto the output.

    If you look deeper the data applied to D first "moves" onto the D output of the master flip flop on the rising edge of the clock. Then on the negative edge "moves onto the output pin, of the slave, Q.

    So if you connect the not Q (inverse Q) output to the D input you will get the waveform as in the above link. Which is dividing the clock frequency by 2 for each D type flop flop connected. Is this what you are trying to explain/prove to yourself?

    All digital devices must receive digital signals 0volts (logic0), or 5Volts(logic1) nothing else. So sine-waves are a no no.

    Don't feel bad about not understanding, its obvious you have a good knowledge of the type of circuit, if a little to inquisitive for your own good ...... :)

    Edit1:
    The main reason for the difference in frequency (divide by 2) is the fact that you need a rising edge and a falling edge for the output Q to change.
    Hope this helps .....
     
    Last edited: Mar 10, 2014
  5. BobK

    BobK

    7,682
    1,686
    Jan 5, 2010
    You are not going the see the freqency difference as output when using random inputs, since random inputs do not have a frequency. Try putting a frequency of 3 times the clock frequency in as the input, and see what you get at the output.

    Bob
     
    davenn likes this.
  6. Dee

    Dee

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    Mar 7, 2014
    frequency division makes sense because i can easily see that. oddly enough the first thing that always pops into my head when thinking 74HC74 is frequency difference. and i have used it one too many times to have any excuse not to know why the hell it's happening.
    sorry about mentioning sine waves. obviously the input into the 74 is squared. i usually start out with sines so they are on my mind; so yeah... "squared sines" (eventually before reaching the magic item 74HC74) :)
    working with different clocks is a great idea. Unfortunately the "Logical Circuit" software does not permit it so i will go on the hunt for another (seems i have acquired a taste for laziness: why do the math when you could be mistaking and softwares look so much more neat than my chaotic handnotes). Thing is i know that inputting a steady clock and a wildly varying (i mean wild as in "no pattern") signal of close frequency still yields the frequency difference. so since steadiness should not be a prerequisite i thought of simply experimenting with random signals in any configuration i could think of.
    originally i was a bit confused of the 74's output thinking that since i am using it as a mixer i might get the intermediate frequency as f1+ - f2 but i know by experiment i got f1-f2 alone without having to filter it.
    ill try running some simulations with different clocks (any suggestion on a good logical simulator?)
    Thanks for your time
     
  7. Dee

    Dee

    5
    0
    Mar 7, 2014
    I found "Logic Gate Simulator" allows modifying clocks period in ms to ones hearts contend. Never liked the circuit look in this software but it is what it is. Hope i did not screw up on connections. Played around with the clocks in any way i could think of. Image 1 is the setup and its output. I then took a screen of the output alone. since its a rising edge i drew black lines onto every rise. Then started doing the subtraction by hand. So on every rising edge i took the value of the upper signal at the time of the rise and subtracted the lower one. So essentially it is either 0-1 or 1-1 since after the rise the lower signal will always be one. Subtracting the first from the second signal would have yielded the same thing according to binary subtraction so no problem there. The red line is what i drew up myself. That according to my brain is what the difference would look like.... almost close but not really....
    so my first question on this one is could you please tell me where i went wrong with the subtraction?
    it would also make sense for the thing (assuming i would have gotten a similar output) to be shifted to the right by 3 pulses since i understand that's how long it takes a master-slave arrangement to produce an output. but as far as i can see the similarities that exist lie three pulses to the left and i don't get why.....
    Again thanks for taking your time with this....
     

    Attached Files:

  8. Dee

    Dee

    5
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    Mar 7, 2014
    mursal i think my problem might lie where you pointed out but i still can not figure it out ... the output changes at the falling edge but the difference is to be computed at the rising edge? - wouldn't that simply yield a shift of the output to the right?
     
  9. Harald Kapp

    Harald Kapp Moderator Moderator

    10,821
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    Nov 17, 2011
    This is not true. Look at the datsheet table 3. It clearly states that the output of the flipflop chnages with the rising edge of the clock.

    A latch is not a flipflop. A latch typically has two states:
    1) transparent
    2) latched
    In the transparent state the output of the latch follows the input signal (with only a small delay).
    In the latched state the outputs is help at the logic level of the input that was present at the time the latch-enable signal went active (often low).

    The difference is that a flipflop does not follow the input signal, neither in the low state nor in the high state of the clock whereas a latch follows during the inactive state of the latch-enable signal.
    A master-slave flipflop can be constructed from two latches in series where the latch-enable is inverted between the two.

    What is an intermediate frequency supposed to mean? For me this doesn't make sense. If you apply two clocks to a flipflop, one to the D-input, one to the clock-input, you will achieve a kind of random looking output signal that depends on the phase-relationship of the two clocks. That's why the "user output" in your last post has low-high cycles of varying length.

    Basically, what you get when the signal frequency at the clock-input is reasonably higher than the signal frequency at the D-input is the same signal as on D only shifted and aligned to the clock-input's edges.
     
  10. Petkan

    Petkan

    19
    2
    Feb 9, 2011
    Petkan:
    '74 is a dual D type flip flop. It has active low SET* and Clear* acting at any time irrespective of D or C.
    If both are active simultaneously - both output become High. If unused they have to pulled High.
    D input is sensitive on the leading edge of C. Whatever its state - it is transferred to Q (and its opposite to Q*).
    frequency division we need to organize this flip flop as counter. This is done by Q* to D connection and input frequency applied to C. Each leading clock edge toggles the flip flop . This makes division by 2. The second instance of '74 can be used for dividing again by two. For higher division ratios look for counters like '90 (decimal) or ;93 (hex) or CD4040 or CD4060 offering embedded clock oscillator and way longer chain of flip-flops inside. For long time delays - see '7541. It features RC clock oscillator and selectable division ratio, selectable outut active low or high etc. Finally - look at Timerblox family LTC699X. They have no timing caps in their oscillators and achieve tighter tolerance
     
  11. Petkan

    Petkan

    19
    2
    Feb 9, 2011
    Petkan:
    Some '74 have non-zero set up or hold time requirements. This means that D has to be stable a bit before and after a clock low to high transition. Directly connecting Q* to D does not guarantee the hold time. A small resistor (with the input parasitic capacitance) like 200 Ohm can make the difference. No harm adding also a small cap to D (to GND).
     
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