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Non-integer dividers.

Discussion in 'Electronic Design' started by Dr. David Kirkby, Feb 9, 2004.

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  1. I'm looking to divide a sine wave (easily converted to square) with a
    divider down to a lower frequency. I'll probably start with about 100
    MHz, and want to get it to about 3 MHz, requiring a division of
    ~100/3=33.3333 The exact division is unimportant, but it is essential
    that it is not an integer. So somewhere between say 31.1 to 31.9, 32.1
    to 32.9 or similar is needed.

    The signal produced by the divider needs to clock an ADC. It is
    *essential* that the rising and falling edges are equally spaced, so
    the ADC get clocked regulary. Quite how often is not that critical,
    but it must be regular.

    Any suggestions how to go about this ???

    Dr. David Kirkby

    drkirkby (at) XXX medphys.ucl.ac.uk
    (ignore the XXX and replace (at) with the the @ symbol).
     
  2. Tilmann Reh

    Tilmann Reh Guest

    You could use a second oscillator generating the 3 MHz and lock it
    to your input frequency with a PLL. This way, about any relation is
    possible.

    If you don't want to use a PLL, simply increase your input frequency
    to i.e. 200 MHz, then devide by two to get back to 100 MHz and divide
    by 67 to get about 3 MHz. The factor between the two output frequencies
    will be 33.5 then.
    You might also consider using even higher base frequencies, depending
    on your technology and if/what you want to do with the 100 MHz.
    If you want equal spacing, first devide to twice the frequency you need
    (about 6 MHz in this case), and then use a single flip-flop two get
    a perfectly symmetrical square wave.

    --
    Dipl.-Ing. Tilmann Reh
    Autometer GmbH Siegen - Elektronik nach Maß.
    http://www.autometer.de

    ==================================================================
    In a world without walls and fences, who needs Windows and Gates ?
    (Sun Microsystems)
     
  3. Tilmann Reh

    Tilmann Reh Guest

    You could use a second oscillator generating the 3 MHz and lock it
    to your input frequency with a PLL. This way, about any relation is
    possible.

    If you don't want to use a PLL, simply increase your input frequency
    to i.e. 200 MHz, then devide by two to get back to 100 MHz and divide
    by 67 to get about 3 MHz. The factor between the two output frequencies
    will be 33.5 then.
    You might also consider using even higher base frequencies, depending
    on your technology and if/what you want to do with the 100 MHz.
    If you want equal spacing, first devide to twice the frequency you need
    (about 6 MHz in this case), and then use a single flip-flop to get
    a perfectly symmetrical square wave.

    --
    Dipl.-Ing. Tilmann Reh
    Autometer GmbH Siegen - Elektronik nach Maß.
    http://www.autometer.de

    ==================================================================
    In a world without walls and fences, who needs Windows and Gates ?
    (Sun Microsystems)
     
  4. Ian Stirling

    Ian Stirling Guest

    PLL?
    Would /31.5 do?
    Simply divide by 63, to get to 1.58Mhz, then use an XOR gate to detect
    changes, and a monostable to get 3.17Mhz.
     
  5. Tilmann Reh

    Tilmann Reh Guest

    With this method, the rising and falling edges would definitely not
    be equally spaced. Additionally, even the output pulses (the edge "pairs")
    would not be equally spaced.

    --
    Dipl.-Ing. Tilmann Reh
    Autometer GmbH Siegen - Elektronik nach Maß.
    http://www.autometer.de

    ==================================================================
    In a world without walls and fences, who needs Windows and Gates ?
    (Sun Microsystems)
     
  6. Ben Bradley

    Ben Bradley Guest

    In sci.electronics.design,
    (Dr. David Kirkby)
    wrote:
    That's an odd (no pun intended) requirement.
    That's easily enough done. Generate a frequency twice your desired
    ADC clock, and run it through a single flip flop.

    Is there some reason the ADC clock needs to be locked (by a
    non-integer factor) to the other 100MHz-or-so signal?
    You can do that with a PLL as others suggested, but it seems that a
    second oscillator at 2x the ADC clock into a divide-by-2 FF will give
    a more stable clock with less jitter and phase noise and such.
     
  7. Ian Stirling

    Ian Stirling Guest

    The rising and falling edges would be equally spaced, but the spacing
    between rising and falling, and falling and rising edges may not be
    the same.

    Why would the output pulses not be equally spaced?
     
  8. Tim Wescott

    Tim Wescott Guest

    A DDS (digital digital synthesizer) driven from your 100MHz clock and set
    for a 3MHz output should, with appropriate filtering, give you a good clean
    50% duty cycle clock. You may do better to divide down to 6MHz and divide
    by two with a plain-ol' flip flop.

    Check the Analog Devices web site for DDS chips -- they should have eval
    boards if you just need a one-off. You could also do a search on "DDS" (or
    "DDS" and "radio") on Google or Altavista -- these things have been taken up
    by the amatuer radio home-brew community, there are a number of assembled
    examples out there to choose from.
     
  9. Jim Thompson

    Jim Thompson Guest

    If we're talking fixed frequencies I'd use a non-linearity-plus-a-tank
    to triple to 300MHz, then divide by 50, then divide by 2 for symmetry.

    ...Jim Thompson
     
  10. gwhite

    gwhite Guest

    Exactly -- find a common multiple.

    Fractional may be a choice these days, since fractional synths are available.
    Properly randomizing and filtering the "extra" (or "missing," depending on pov)
    pulses is the biggy. Golberg's book is good on this.
     
  11. Jim Thompson

    Jim Thompson Guest

    Can you elaborate on --^^^^^^^^^^^^^^ ?

    I'm looking for a good text on fractional-N synthesizers.

    ...Jim Thompson
     
  12. mikem

    mikem Guest

    non-integer implies multiplying first, then dividing.
    Symmetry implies a final divide by two (flip-flop)

    eg ((100Mhz * 3)/50)/2) would do it...

    Tripling requires a Phase Lock Loop, or a simple "tripler" tuned-
    amplifier where the output tank circuit is tuned to 300Mhz.

    Dr. MikeM
     
  13. Tilmann Reh

    Tilmann Reh Guest

    That's what I meant.
    Due to the odd division and the XOR edge detector.
    (The odd division can't have a 50% duty cycle.)

    --
    Dipl.-Ing. Tilmann Reh
    Autometer GmbH Siegen - Elektronik nach Maß.
    http://www.autometer.de

    ==================================================================
    In a world without walls and fences, who needs Windows and Gates ?
    (Sun Microsystems)
     
  14. Ian Stirling

    Ian Stirling Guest

    Oops.
    I somehow managed to forget about that.
    Thanks.
     
  15. gwhite

    gwhite Guest


    Sorry for the typo. The text is written by Bar-Giora Goldberg. There isn't a
    ton on fractional itself, but DDS, accumulators, lookup tables, ROM compression,
    and ectetera are included. As Goldberg states, "Fractional division has already
    been demonstrated in the introduction to DDS (which is capable of generating
    frequencies given by WF_ck/ACM -- maximum states of the accumulator), and
    Sections 4-2 and 4-3, and the same principles apply to PLL. Fractional-N
    synthesis can and should be viewed as a combination of PLL and DDS principles."

    In any event, the book is the only synthesis book I have that really covers DDS
    and fractional. It also includes the original Tierney, Rader, and Gold paper.

    What I have:
    http://www.amazon.com/exec/obidos/t...f=sr_1_5/102-5140977-4485701?v=glance&s=books

    He has a newer one I don't have and have not seen:
    http://www.amazon.com/exec/obidos/t...f=sr_1_1/102-5140977-4485701?v=glance&s=books

    For a free-be, look for:

    TI Technical Brief SWRA029
    Fractional/Integer-N PLL Basics
    Edited by Curtis Barrett, Wireless Communication Business Unit
     
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