R
ratztafaz
- Jan 1, 1970
- 0
HI,
on our PCB there is a LED directly connected to a Virtex5 I/O pad. The
LED is connected through a series resistor to 3.3 V. As it seems
Virtex devices do not support open-drain outputs.
If I drive a zero on that output there will be current flowing from
the 3.3V through the LED into the FPGA. Does the FPGA tolerate that?
Which I/O standard/fashion should I use?
regs, Heiner
on our PCB there is a LED directly connected to a Virtex5 I/O pad. The
LED is connected through a series resistor to 3.3 V. As it seems
Virtex devices do not support open-drain outputs.
If I drive a zero on that output there will be current flowing from
the 3.3V through the LED into the FPGA. Does the FPGA tolerate that?
Which I/O standard/fashion should I use?
regs, Heiner
