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Newbie: Datasheet timing diagrams and timing variation

Discussion in 'Electronic Design' started by Richard, Nov 29, 2004.

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  1. Richard

    Richard Guest


    Taking for example a microcontroller reading a RAM device - the datasheet
    for both the microcontroller and memory show 'best and worst' case timings
    for the bus signals. For example the RD~ line will go active between 2ns
    and 6ns after the clock edge.

    When will this variation occur?

    Is it ...

    Always the same for every identical device in that for one device the RD~
    line will always go active 4ns after the clock edge on *every* bus access
    while another device (same part number) it might *always* be 6ns for every
    clock cycle. In this case the timing for each device are different, but the
    timing within the same device is always the same.

    or ...

    Will this variation be seen on a single device - in that taking a single
    device the RD~ may go active 3ns after the clock edge for one cycle, and
    then 4ns after the clock edge on the next. In this case there is variation
    even in one particular part.

    Whichever is the case for microcontrollers, is the same true of FPGA's.

    Thanks for any comments!
  2. Andrew Holme

    Andrew Holme Guest

    Supply voltage, temperature and clock rise time are probably significant.
    The memory address being read and the addressing mode could have a bearing.
    Manufacturing tolerances within and between batches may also factor.
  3. Active8

    Active8 Guest

    When you don't want it to.
    Yeah. Any parts in the batch that don't meet the specs are tossed
    That too is possible. If nothing else, current and temperature will
    affect certain specs. Notice digital part specs are given for
    different Vdd's, also.
    A bus timing diagram is a bus timing diagram... and addressing mode
    doesn't change the specs, but you have to "account" for it when you
    program real time apps.
    An IC is an IC :)
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