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New problems with the solved RS-latch problem

Discussion in 'Electronic Basics' started by Rikard Bosnjakovic, Jan 20, 2006.

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  1. I have now solved the problem with the SR-latch, but I ran into a new
    problem (which regards what I think is oscillation) instead.


    Block-circuit for this project:


    ------------------------- --------------------------
    1 | Triggers (S1, S2, MR) | ---> | SR-latches (trig-lock) | --->
    ------------------------- --------------------------

    --------------------------------------------------------
    1 ---> | OR-gate (made of two diodes and a pulldown resistor) | -->
    --------------------------------------------------------

    -------------------------------------
    2 ---> | 555-trigger (monostable, 50 secs) | --->
    -------------------------------------

    ----------------------------------------
    2 ---> | 555-trigger (astable, 50% duty, 1Hz) | --->
    ----------------------------------------

    -------------- ----------------
    2 ---> | Mech relay | ---> | "Alarm-lamp" |
    -------------- ----------------


    Block 1 and 2 works as a charm separately, but when connecting them
    together the both (actually one, but it triggers the other
    automatically) 555:s just for a second and then the SR-latches gets
    reset and they in turn resets the 555:s.

    I don't have a scope so I can't dive down into the circuit and see
    what happens and where, but I *think* the 555s cause a heavy
    oscillation for the Vcc- and GND-rails that makes the RS-latch spike
    on its R-input, and resets the outputs.

    On play-hookey.com I read about the OR-gate I made (a DL-gate,
    diode-logic gate) and it said that DL-gates sometimes can cause a lot
    of distorsion in signals. Therefore I tried to use a "real" OR
    (74LS32) instead.

    The error did however remain for the 74LS32 as well. The 555s run a
    second or two and the whole circuit gets reset. I tried to add a cap,
    sized 100nF, to the output of the 74LS32 to see if it was the OR-gate
    that wasn't able to fully source the 555. When I did this, the circuit
    seemed to work fine. I'm not sure this means there was oscillation in
    the circuit, since I haven't been able to dive down under the hood and
    investigate because the lack of a scope.

    Conclusion: If I use a proper OR-gate and add a cap, the circuit works.

    But, the problem in doing this are two. First of all, I would rather
    not waste a whole IC just for a simple gate, and second of all there
    will most likely not be enough room on the veroboard which this
    circuit will be residing after the prototyping is done. The space
    where the veroboard will be is physically very limited, and that's the
    reason I reached out for the solution to build an OR-gate of my own.

    What I'm now wondering is if anyone, with the scenario above in mind,
    can take a good guess in why the RS-latch is acting as it does when I
    use my homebrewed OR-gate, or what on earth is resetting the circuit.
     
  2. John Fields

    John Fields Guest

     
  3. John Fields

    John Fields Guest

    ---
    What strikes me immediately is that the monostable isn't being
    triggered properly. What it's looking for is a short, low-going
    pulse on the trigger input which doesn't last as long as its output
    pulse. Also, the circuit can be implemented without the latch, I
    think. I'll work on it and post back in a little while.
     
  4. John Fields

    John Fields Guest

    ---
    Here ya go... :)


    Vcc Vcc
    | |
    [1K] [10K]
    | |
    +--[0.1µF]--+--> TO U1-6
    |
    |
    | O--+--O |
    BELL (NO) | | MAIL (NO)
    | O--+--O |
    |
    |
    Vcc |
    | |
    [1K] |
    | C
    |O--+--B
    DOOR (NC)| E
    |O--+ |
    | |
    GND GND
     
  5. John Fields

    John Fields Guest

    ---
    Looking at your schematic again, it may be even simpler than shown
    above. Something like this:

    Vbat Vbat
    | |
    [1K] [10K]
    | |
    +--[0.1µF]--+--> TO U1-6
    |
    |
    | O--+--O |
    BELL (NO) | | MAIL (NO)
    | O--+--O |
    |
    |O
    DOOR (NC) |
    |O
    |
    GND

    That is, if I'm reading the logic right.

    What I get from the schematic is that if the DOOR switch is closed,
    then when either the MAIL or the BELL switch is closed, you want an
    alarm cycle to start. However, if the DOOR switch is open you want
    the other switches do be disabled and prevented from starting an
    alarm cycle if either one (or both) is pressed. Right?
     
  6. Jasen Betts

    Jasen Betts Guest

    maybe you beed powersupply decoupling, try putting 100nF capacitors between
    VCC and ground on yourr chips.
     
  7. ehsjr

    ehsjr Guest

    You want to operate a relay for ~ 50 seconds when either the door
    or the mail button is pressed? If so this will save you a bunch
    of PCB area vs the or-latch-timers:

    1N4001
    +12 ----+---+------+------|<-----+
    | | | |
    o o | G6RN-1-DC12 |
    / / +---[Relay]---+
    o o |
    | | c/
    +---+-----+---[100K]----| 2N6427
    | | e\ NPN Darlington
    --- | |
    1000uF --- [1M]<---+ |
    | | | |
    | | | |
    Gnd --------+-----+------+-------+

    Adjust the pot for the duration you want.

    Ed
     
  8. As soon as the door-switch is opened, the alarm timer (if started) should
    be stopped. It does not matter if the alarm gets started if the bell or
    the mail-switch gets closed while the door is open, because as soon as the
    pulse from bell and mail stops (they can't be "locked", thus shooting a
    pulse only), the alarm will stop immediately.
     
  9. John Fields

    John Fields Guest

    ---
    That's a completely different problem, but one which can be solved
    by using the door switch to reset the timers in the 556, like this:


    Vbat Vbat
    | |
    [1K] [10K] +---- - - -
    | | 6|_
    +--[0.1µF]--+-----O|T1
    | |
    | |
    | O--+--O | |
    BELL (NO) | | MAIL (NO) |
    | O--+--O | |
    | |
    GND 4|_
    +--O|R1
    ____ | 10|_
    Vbat---O O--+--O|R2
    DOOR | |
    | +---- - - -
    [10K] 556
    |
    GND

    However, in reviewing your schematic again, I found some more errors
    which I'll correct, then I'll post a new schematic to abse later on
    today.
     
  10. John Fields

    John Fields Guest

     
  11. ehsjr

    ehsjr Guest

    <snip>

    Here's a revised circuit, after you added that opening the
    door should shut the alarm relay off immediately:


    1N4001
    +12 -+-----------+---+------+------|<-----+
    | | | | |
    | o o | G6RN-1-DC12 |
    | M/ D/ +---[Relay]---+
    [1K] o o |
    | | | c/
    | +--|<--+---+-----+---[100K]----| 2N6427
    | | | | e\ NPN Darlington
    | c/ --- | |
    +---| 1000uF --- [1M]<---+ |
    | e\NPN | | | |
    o | | | | |
    door | | | | | |
    o [100R] | | | |
    | | | | | |
    Gnd -+----+----------+-----+------+-------+

    (door switch shown with door closed)

    With the door closed, pressing either the Mail (M)
    button or the Door (D) button will charge the 1000 uF
    cap rapidly. That will turn the darlington on to operate
    your alarm relay. The darlington has huge gain - at least
    10,000 - so it will discharge the cap slowly through the
    100K resistor. The discharge time - and therefore the
    time the relay will stay energized - can be shortened to
    ~ 50 seconds by adjusting the 1M pot, which provides a
    second discharge path for the cap. As long as the door
    is closed, the base of the NPN on the left is held at gnd,
    so the transistor is off and does not affect the circuit.
    When the door is opened, the transistor is turned on, and
    discharges the 1000uF rapidly.

    Ed
     
  12. John Fields

    John Fields Guest

     
  13. ehsjr

    ehsjr Guest

    Ahhh. I didn't realze that's what he wanted. Thanks!

    Ed
     
  14. John Fields

    John Fields Guest

     
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