NEED UNDERSTAND OF PCI TIMING

[RAMSELECTRONICS]

I read the book and website, I am still bit not understanding. (I am not good reading books)

I understood about the IO-READ and IO-WRITE from the C/BE command.

I am struggler to understand how to get ADDRESS and DATA PHASES.

This what I thought:
FRAME=low, IRDY=high, TRDY=high, DELSEL=high is ADDRESS PHASE
FRAME=high, IRDY=low, TRDY=low, DELSEL=low is DATA PHASE

Is that right?

 

[JimW]

That isn't really the way to look at the problem. You need to count the clock edges from certain events. The first clock period after Frame goes active is the Address phase. Each clock period that IRDY and TRDY are active are successive data cycles. DEVSEL is returned by the target that is addressed, it can be used as a qualifier for the data cycles on read and is necessary for writes. IF you try to do this combinatorially, you will be looking for trouble. The PCI bus is intended to be a clock synchronized bus and the logic interfacing it should be done that way.

-Jim