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need small PAL with SR latch

Discussion in 'Electronic Design' started by colin, Jun 24, 2005.

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  1. colin

    colin Guest

    I tried this, it cleverly sees theres a SR latch here and goes ahead and
    uses one but then gives an error :-
    'xxx devices do not have latch with both async set and reset. Fitter may
    fail' (wich it does)

    Il gues il stick to schematic entry as this seems to work although I still
    havnt figured out how to stop it using negative logic on the outputs with
    some devices.

    Colin =^.^=
  2. keith

    keith Guest

    Crap. I've never had enough pins. Even an FG680 ran out of pins (five
    years ago).
    It's not just "easy" it's "possible".
    Actually, no they don't. You have no idea whether your routing this time
    is the same as last. Metastapility is a horrid thing when you have no clue
    what your feedback time is. That's just one of the heads of the FPGA
    Not so, grasshopper. It's not even possible to know. All you're doing is
    opening the window of death. ...and not knowing how wide!
    Naw. We haven't gotten there yet. Clocks are still distributed in a sane
    manner and even taken care of in the timing analysis. add your
    loops, and all bets are off!
    The may be, but I doubt it. As Iv'e said, these are an anethma to logic
    design. ...not to mention test.
    VHDL *is* essentially a multi-threadded language. The point of the
    PROCESS statement is to serialise execution. The last to set a
    signal/variable in a process rules though (bottom to top, as it were).
  3. keith

    keith Guest

    You don' thave the latch in the library (which I suspected). It appears
    that it's not smart enough to make one out of gates. Synplify would, but
    bitch like hell doing it. There is a difference in tools.
    Look at you IOBs. You may have an IOB that has an implied inversion. The
    Xilinx IOBs were a littttle crazy with OE's, it wouldn't surprise me that
    Altera had similar nonsense.
  4. colin

    colin Guest

    Thanks, I'm using Lattice as Altera doesnt seem to do the small parts,
    it seems to use the synplify compiler for vhdl, but im just using the
    schematic input method now as that seems to produce a fit in the small parts

    Ive looked at the IOB on the data sheet and although they have inverted
    outputs there is an xor with one input set high or low wich shld enable
    selection of active low or active high outputs, both the 16v8 and 22v10 have
    inverted outputs with an xor stage and one comes out inverted (q apears as
    !q next to the relavent pin on the generated pinout diagram) the other
    doesnt, im not sure if I should acount for that in my equations or not. i
    think i might be able to figure it out from the jedec file, heck il probaly
    end up just writing the jedec file.

    Ive looked through the help files however many of the menus/icons I tried to
    folow are greyed out wich probably means i need to go and look for more
    modules to instal or something. it says something about a constraint editor
    but the only option i have is to import a constraint file not edit it.

    Colin =^.^=
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