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Need help writing VGA Driver

Discussion in 'Microcontrollers, Programming and IoT' started by Jeremy, Jun 4, 2013.

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  1. Jeremy

    Jeremy

    5
    0
    Jul 9, 2012
    Hello,

    this isn't particularily for programming a microcontroller, rather an FPGA. I wasn't sure where to post it, so I'm going to post it here.

    I am trying to write a 640x480 vga driver in verilog. I am analyzing a working VHDL module and following this ( http://people.ece.cornell.edu/land/courses/ece4760/FinalProjects/s2012/raf225_dah322/raf225_dah322/ ) as a guide. The problem is that I am just getting a black screen, the monitor is picking up the VGA signal, but it is not rendering any image onto the screen (I am seeking a totally white image on the screen.)

    I have tried the other module and plugged it into my FPGA. It function perfectly, which implies that the wiring is proper.

    I have compared my waveforms in a modelsim simuation to that which I know works perfectly and I still am unable to get anything other than a black screen.

    I don't expect you to analyze this verilog code line for line (since there are a lot of unnamed constants) but I would appreciate it if you looked at the produced waveforms in a simulator and assure it is proper. Further, maybe if you tried plugging this into your own development boards?

    Is it at all possible that quartus is not synthesising my verilog code properly due to some faulty configuration on my part? I'm not super familiar with quartus.

    Here is my verilog code, I appreciate your insight:

    Code:
    module vgaDriver(
    	clk50M,
    	reset,
    	hsync,
    	vsync,
    	red,
    	green,
    	blue);
    	
    input clk50M;
    input reset;
    
    output hsync;
    output vsync;
    
    output red;
    output green;
    output blue;
    
    wire clk50M;
    
    reg [20:0] countV;
    
    wire hsync;
    wire vsync;
    
    wire red;
    wire green;
    wire blue;
    
    initial
      begin
        countV = 833039;
      end
    
    always @(posedge clk50M or posedge reset)
    	if (reset) begin
        countV <= 833039;
    	end
    	else begin
    		countV <= (countV + 21'd1) % 21'd834642;
    	end
    
    assign hsync = (countV % 1602) >= 192;
    assign vsync = countV >= 3204;
    
    assign red = countV > 60878 && countV < 818629 && (countV % 1602) > (192 + 94) && (countV % 1602) < (192 + 94 + 1280);// && countV % 4 >= 2;
    assign green = red;//(countV % 250 > 100);
    assign blue = red;
    
    endmodule
    
     
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