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need help with timing issue on an astable

Discussion in 'General Electronics Discussion' started by thomoj, Nov 7, 2013.

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  1. thomoj

    thomoj

    4
    0
    Nov 7, 2013
    hi i have built a standard astable with a 555

    i needed the time period to be 30s

    when i built it with reset (pin 4) to the high rail, it gave me a time period of 30seconds

    however i needed the astable to be powered from a logic gate (7400 series nor gate)

    when i connected reset pin 4 to the output of the logic gate, the initial time period changed to 45s but subsequent pulses were 30s.

    i tried connecting pin 8 from the high rail to the logic gate output and reset to the high but this gave me a constant time period of 23s, im sure this should not be happening! any help?

    circuit powered by 5v, and have tried using a mosfet from the logic gate output, no change, and have tried a 4000 series nor gate and swapped my 555, no change.
     
  2. KMoffett

    KMoffett

    723
    75
    Jan 21, 2009
    When a 555 astable is normally oscillating, the timing capacitor ramps back and forth between 0.66 Vcc and 0.33 Vcc. Pulling the reset pin low discharges the timing capacitor to near 0V. So when you release the reset pin, that first time period is determined by the capacitor ramping from 0V to 0.66 VCC, not 0.33 Vcc to 0.66Vcc. So, it will be longer than the normal astable period you set.

    Ken
     
  3. thomoj

    thomoj

    4
    0
    Nov 7, 2013
    That makes sense, thank you ken, is there any possible way around this for my low frequency astable? Or should i just deal with it
     
  4. BobK

    BobK

    7,682
    1,688
    Jan 5, 2010
    I think that is expected, because the capacitor has to charge from 0V to 2/3 Vcc instead of 1/3 Vcc to 2/3 Vcc.
    The output of the logic gate is probably not high enough to power the '555 reliably.

    Bob
     
  5. thomoj

    thomoj

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    0
    Nov 7, 2013
    Cheers bob
     
  6. thomoj

    thomoj

    4
    0
    Nov 7, 2013
    Just wondering, why is the time period what i want when 4 is connected to the high rail then
     
  7. KMoffett

    KMoffett

    723
    75
    Jan 21, 2009
    When you connect pin 4 high, the "reset" function that I described in post #2 is disabled. The timing is then set by internal comparators.

    Attached is a circuit I designed that turns the astable off by clamping the timing capacitor at 0.33 Vcc. When your logic activates the astable, the timing voltage starts at 0.33 Vcc, not at 0.0 V as when you use pin 4. The selection of R3 and R4 is made so their junction is 0.33Vcc. Their values should be on the order of about 100th to 1000th the values of you timing resistors, R1 and R2. The BS108G is a Logic Level N-channel MOSFET. Your TTL logic can directly drive it's gate. High enables the 555. The 555' circuit must always be powered.

    Ken
     

    Attached Files:

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