Here's a simulation of the exact circuit you've drawn up, excluding the regulators. I'm describing the high-voltage rail as "bootstrapped" because BR1 uses the transformer secondary voltage directly, and BR2 uses the transformer's output voltage again, to add more voltage on top of that, which in some sense can be described as bootstrapping, in the electronic sense of the word.
I had to draw the bridges out as discrete diodes. LTSpice doesn't have a bridge rectifier as standard; I found one in a library but I couldn't figure out how to include it easily, so I gave up.
I've added RL1, RL2 and RL3 as load resistors to draw 0.5A from each low-voltage rail, and 0.1A from the high-voltage rail.
It's actually pretty important to know the maximum current you will be drawing from each of these rails. It affects the capacitor values you will need. The value of C11 has implications for C9 and C10 as well, as I'll explain below.
Here's a graph of the voltages on V1, V2 and V3.
You can see that there's a fair amount of ripple on all the rails. This could be reduced by increasing the relevant output smoothing capacitor, but as long as the trough in the ripple is comfortably high enough (including tolerances on transformer ratio, AC mains supply voltage, and anything else), you don't have to.
The graph above shows the AC voltage at point "S1" (the top end of the secondary), and the CURRENTS through C9 and C10. This is important, because current only flows in these capacitors for a short time, as you can see.
The upward spikes on the blue and red traces represent C9 and C10 (respectively) being CHARGED from the transformer. The downward spikes represent them being DISCHARGED into C11.
As you can see from the scale on the right side, the positive and negative peaks are both about 0.5A. That is with a load of only 100 mA on the V3 rail. So with the component values you originally specified, the peak positive and negative ripple currents in C9 and C10 are about five times the load current on the V3 output.
This is significant because ripple current can (and does) damage electrolytic capacitors in the long term, and you should investigate the ripple current specificaitons of the capacitors you use for C9 and C10.
I started writing this post yesterday, but I'm not going to be able to finish it for a couple more days, so I thought I should post what I have so far. I will run some more simulations with different values of C9/C10 and C11 to see what would be the best approach to minimise stress on C9/C10. I will probably recommend adding some small-value resistors in series with them (something in the range 2~10 ohms or so) to reduce the peak currents.
In the meantime it would be helpful if you could specify the maximum expected current drain on the three voltage rails.