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Need help about CMOS domino logic

Discussion in 'Electronics Homework Help' started by dhlee, Oct 15, 2014.

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  1. dhlee


    Aug 27, 2014
    Here is the Logic, I forgot to add Z(output) out of the NOT Gate.
    Anyway, I understood that Dynamic Logic is controlled by MOSFET's internal capacitance,

    I thought MOSFET A-E's internal capacitance will charged, but I knew that this is not correct
    (I didn't know that PZ has parralel capacitor.)

    if this right, I thought that when Φ is 1, Capacitor PZ discharges to left N-FET, Z(output) is on, even Φ is 1 cause Z's capacitor(like PZ Cap).

    And another question.
    if A,B is closed and left P-fet off,N-fet on -> Can PZ cap discharge? Cap will have GND to any side.
  2. Harald Kapp

    Harald Kapp Moderator Moderator

    Nov 17, 2011
    I may not fully understand the phrase. But: consider the logic gate pe se (i.e. without the buffer-inverter). The logic function is PZ=(A*B)+(C*(D+E)) where *=AND and +=OR.
    When Φ = 1, this logic function is evaluated, PZ takes on the respective logic state and the buffered output of the gate is NOT(PZ).
    When Φ = 0, the lower left NMOS is off, the upper left PMOS is on. PZ is pre-charged to logic 1, leafing the output NOT(PZ)=0.

    In the gate(s) attached to the output of this gate this will turn off all NMOS input transistors. Only when Φ goes high again will the output of this gate change state according to the logic function and the inputs of the following gates will follow suit.


    By the way: this smells like homework. If so, I can move it to the correponding forum section and I kindly ask you to post in the right section next time.
  3. dhlee


    Aug 27, 2014
    I understood it.
    Z(Output) also has virture CAP, so it charges output and discharge while PZ is over right P-FET's threshold V.

    So the answer is A.B + C.(D+E)
    thank you for your advice.
    and I'll find correct forum section next time
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