Narrow pll loop filter

[[email protected]]

Hello,

I'm trying to design a PLL with narrow loop filter, about 10Hz. The
most popular (2nd order)
designs are active PI filter and pasive RC filter, but calculations
gives me mF capacitors and mOhm
resistors. I see, that phase shift for DC very low freq. in by PI
filter is
about 90 deg. I think that Bessel or Czebyshev (with slowly changing
phase shift, without instant "phase jump")
filter would be great, but these filters produces different phase
shifts for near-DC component and I don't know,
if phase loop will work. Also filters like MAX280 are very convenient.
Does anyone know, how to build shuch a filter?



E.C.

 

[Vladimir Vassilevsky]

Hello,

I'm trying to design a PLL with narrow loop filter, about 10Hz.

What do you mean exactly? Is 10Hz a desired close loop noise bandwidth
or what?

The
most popular (2nd order)
designs are active PI filter and pasive RC filter, but calculations
gives me mF capacitors and mOhm
resistors.

Looks like the excessive open loop gain, so the poles have to be located
at very low frequency.

I see, that phase shift for DC very low freq. in by PI
filter is
about 90 deg. I think that Bessel or Czebyshev (with slowly changing
phase shift, without instant "phase jump")
filter would be great, but these filters produces different phase
shifts for near-DC component and I don't know,
if phase loop will work.

Avoid the higher order filters in the PLL unless you really need them.
It complicates the situation dramatically.

Does anyone know, how to build shuch a filter?

Try dropping the loop gain.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

 

[[email protected]]

What do you mean exactly? Is 10Hz a desired close loop noise bandwidth
or what?

I want to measure phase noise of generator using low noise VCO tuned
by PLL (as described in HP/Agilent Product Note 11729B-1 "Phase Noise
Characterization
of Microwave Oscillators"). In quadrature, at phase detector output I
will see sum of two noises: from VCO and DUT (my generator). But
tracking phase loop
will suppress phase noise inside loop filter bandwidth, so this
filter should be very narrow loop (eg. 10Hz or less).
My generator is quite stable, it drifts very slowly, and I think that
10Hz will be enougth to hold the lock of tracking loop.

Looks like the excessive open loop gain, so the poles have to be located
at very low frequency.

It is too complicated for me, I'm not familiar with Laplace
transform :-(

Try dropping the loop gain.

It sounds very good, I'll build a simple divider on low noise opamp
with 1/10-1/20 gain.
At now, VCO gain is about 5e6 Hz/V, D.U.T. works at 80MHz, and Kd is
0.46 rad/V.

Thanks,

E.C.

 

[Allan Herriman]

Hello,

I'm trying to design a PLL with narrow loop filter, about 10Hz. The
most popular (2nd order)
designs are active PI filter and pasive RC filter, but calculations
gives me mF capacitors and mOhm
resistors.

This is a fundamental problem with this sort of PLL.
There are two parameters you can vary: the time constant of the zero,
and the gain (which sets the pole locations). You can often do
something about the gain (by changing the reference and feedback
dividers, or the phase detector current), but the zero can be a hard
nut to crack.

The time constant (i.e. RC product) associated with the zero will need
to be around 5-10ms to get that closed loop bandwidth, for a
reasonable damping ratio.

(For at least part of the output spectrum) the output phase noise is
determined by the resistor value (from en = sqrt(4kTR) V/sqrt(Hz)), so
you want to keep the resistor value as low as you can.
Work backwards from your phase noise specification to get the maximum
allowable resistor value. If it's 1Mohm, good. If it's 1kohm, you
might have problems as the cap gets unreasonably large.

But you also want to avoid large capacitors, as low leakage types get
expensive and physically large. Al or Ta caps are cheap, but have
leakage current, which might cause a unacceptably large steady state
phase error. Hi-K ceramic caps can have microphonics (which may cause
hard-to-debug phase noise at the PLL output). Low-K cermic caps are
only available up to a few uF or so, and are expensive.


I tend to go for passive loop filters (I'm that kind of guy). In the
past, I've used Wima metalised film caps to 1uF. The very last time I
designed a PLL (for a SONET clock), I got lazy and just used a 10uF
X5R cap that was already in the CAD library. It worked fine.

Regards,
Allan

 

[Howard Swain]

Hi E.C.,

I want to measure phase noise of generator using low noise VCO tuned
by PLL (as described in HP/Agilent Product Note 11729B-1 "Phase Noise
Characterization
of Microwave Oscillators"). In quadrature, at phase detector output I
will see sum of two noises: from VCO and DUT (my generator). But
tracking phase loop
will suppress phase noise inside loop filter bandwidth, so this
filter should be very narrow loop (eg. 10Hz or less).
My generator is quite stable, it drifts very slowly, and I think that
10Hz will be enougth to hold the lock of tracking loop.



It is too complicated for me, I'm not familiar with Laplace
transform :-(


It sounds very good, I'll build a simple divider on low noise opamp
with 1/10-1/20 gain.
At now, VCO gain is about 5e6 Hz/V, D.U.T. works at 80MHz, and Kd is
0.46 rad/V.

Do you mean your VCO gain is 5 MHz / V ?
That would be very sensitive.
I'd think you'd need a crystal oscillator (or something referenced to a crystal)
for both sources to even think about measuring that close in. But I could be wrong.