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mux / serdes design

Discussion in 'Electronic Design' started by Leroy Tanner, Nov 11, 2004.

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  1. Leroy Tanner

    Leroy Tanner Guest

    Dear newsgroup readers,

    I am currently working on a multiplexer design in VHDL. For the time being
    the design should run on a Xilinx Virtex II FPGA but actually I am not
    concerned about any target device later on. My question is more general.
    What I want to do is multiplex four input signals into one output signal,
    meaning that there are four parallel inputs that should merge into one
    serial output. Therefore the output must be four times faster than the
    input, right? I see problems in generating the faster clock out of the
    master clock of the slower inputs, that means I HAVE TO provide the fast
    clock for the serial output right away and then transform it back to the
    slower to handle the input, is that right?
    What's more I want to multiplex the signals byte-wise. How can that be
    achieved WITHOUT wasting a great amount of registers? And how to manage the
    data being transfered between the two clock domains?

    Regards, Leroy
     
  2. If I understand you, you're proposing a 4-bit parallel load shift
    register.
    You have to shift the register at four times the input, yes.
    Not necessarily. Depending on the frequency, you may take advantage of
    the DLLs in the clock generators (I think Xilinx calls them DCMs) to
    create the 4X clock out of your input, or the other way around (1/4x
    from the higher speed clock).
    As I see it, the cheapest way to do this is eight four-bit shift
    registers, perhaps with a register in front. Depending on your
    requirements, you may be able to get away with moving the input
    register into the IOB, leaving you with 32 flops used, which isn't all
    that much for a Virtex II.
    I don't understand the question. You need to be more explicit with your
    requirements. What exactly is it that you're trying to do? What are
    your constraints?

    Make sure all of your clocks are synchronous. Perhaps add a signal to
    the output stream to signal the start of data (mux data 0 valid).
     
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