# Multi-input D flip-flop?

Discussion in 'General Electronics Discussion' started by LateBlt, Sep 14, 2015.

1. ### LateBlt

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Sep 14, 2015
Hi everyone, I have what I really thought would be a simple question, but I have not been able to find information on this anywhere on the Internet, and I was wondering if anyone here could shed some light on this matter. Is there no such thing as a multi-input D flip-flop? As we all know, a D flip-flop usually has only one D input which carries the data (and a second "Activate" or "Clock" input which causes the flip-flop to store the data input), but what if I want a flip-flop which can receive data from 2 different sources? What I'd like is a 2-input or ideally a 3-input D flip-flop, one with 3 D inputs and 3 Clock inputs which, when activated, will store the value of any of 3 wires in the flip-flop. Has no one ever seen such a circuit before? Thanks in advance for any ideas.

2. ### Old Steve

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Jul 23, 2015
Why not connect your 3 inputs to the one 'D' input with diodes, like in my sketch:-
(Standing on their ends, 3 x 1N4148s wouldn't take up much space.)

For multiple clocks, they could be connected the same way - 3 more diodes.

3. ### Old Steve

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Jul 23, 2015
That was a diode 'OR'.

For reference, in case you ever need it, you can create a diode 3-input 'AND', too, by reversing the diodes and connecting the resistor to +V instead of GND:-

4. ### LateBlt

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Sep 14, 2015
Hmm, the problem with that is that it would still be triggered by just one Clock input, and there isn't any way to tell which of the inputs is on or not. You can do an OR or an AND this way, but you can't really single out a specific input, which is necessary if you have three different data sources that you need to individually select from.

5. ### eetech00

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Nov 17, 2014
Not sure what your trying to accomplish but why not just use three D flip-flops?

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8. ### AnalogKid

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Jun 10, 2015
I think I know what you are asking about. For a long time I've wished for a chip like a quad logic gate that had four independent, stripped-down D flipflops in one 14 pin package: 4 D inputs, 4 clock inputs, 4 Q outputs. A 74LS279 comes close as a quad S-R.

ak

9. ### BobK

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Jan 5, 2010
It is not at all clear how you want this to act. Here is my guess:

You have 3 inputs, 3 clk pins and 1 output.

When any clk pin goes high (or whatever), the data from the corresponding input is latched.

Is this right?

Bob

10. ### AnalogKid

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Jun 10, 2015
If you think through your description, you'll see that it is not complete. Either that or it is simply a single ff and some OR gates.

ak

11. ### Old Steve

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Jul 23, 2015
If you only have the one flip-flop, with one output, why would you need to single out a specific input? And if you need to single out a specific input, one flip-flop isn't enough. As mentioned, your description is lacking. Draw a simple circuit with your supposed flip-flop, showing it's use, and how you can 'single' out one of the inputs when there's only one output.

12. ### LateBlt

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Sep 14, 2015
Sorry if my request is unclear... I don't have the ability to draw a circuit up right now, but all I want is a D flip-flop with 3 inputs and one output. BobK basically had it right: The D flip-flop would have 3 wires going in, and it would need to be programmed from any of those 3 inputs. Then the output would retain the state of that input. I'm asking because in a digital system, often there is more than one internal data bus, and so a register needs to get its input from more than one source.

13. ### Old Steve

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Jul 23, 2015
Yeah, hence the three diodes. A diode OR.

Don't you have 'Paint' or similar on your machine to draw a diagram? Only takes a minute or two.

14. ### LateBlt

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Sep 14, 2015
I made a diagram, but I don't know if it makes things any clearer:

I think what might help more is a truth table, so I went ahead and made one in Excel. (This is a table for a 2-input D flip-flop to keep things simple, but I hope that it makes it clear what the idea is. A 3-input D flip-flop would work the same way except with an additional data input.)

Basically, only one Clock input should ever be active at a time, and if more than one is active at a time, then that's an invalid input, similar to what happens if you turn on both inputs to an S/R flip-flop simultaneously.

I can't use a multiplexer or anything like that because the point is that there's supposed to be only a single output and that the device can be "clocked" or "activated" with just a single input. It seems like a fairly straightforward idea to me, so I'm surprised that I've never seen a description of any such device. I hope that everything is clear now.

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15. ### Old Steve

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Jul 23, 2015
The way to achieve something like this in only one chip would be a PLD, I think. Never used one, but I asume they have flip-flop functions.Otherwise, a single flip-flop, with diodes as described earlier, and a multiple-input XOR driving the clock input. (2 chips)

There's not enough call for something so specialised for manufacturers to go into production, but it's easy to get the function with 2 chips.

Edit: In fact, even the 3-in XOR would be no good since any one clock would clock any of the data. A PLD would be best, or a combination of other logic chips, like 3 flip-flops into 3 diodes and then linked.

Or my favourite, a small micro. Something cheap like an 8-pin PIC12C508. I have some here, including the windowed UV-erasable ones for prototyping. (12C508s are OTP, but there would be a modern flash equivalent.) Not enough pins - only 6 available and we need 7, so I'd use a PIC16F84.

Last edited: Sep 15, 2015
16. ### LateBlt

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Sep 14, 2015
It could definitely be done with a bit of custom logic; I was hoping to avoid having to implement a custom IC into the plans, but it looks like you're right and that's the only way to do it without making things unnecessarily complicated. Thanks for the advice, and yes, those little PIC chips are sure useful for little hacks like this.

17. ### Old Steve

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Jul 23, 2015
Yep, nice and cheap too. \$4 from Hong Kong for a PIC16F84A:-
http://www.ebay.com.au/itm/1pcs-PIC...8-pin-NEW-m-/180718425788?hash=item2a13a856bc

18. ### Harald KappModeratorModerator

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Nov 17, 2011
What would you use such an FF for? You'll never know from the state of the Q output where it comes from (the combination of D1/Clk1 or D2/CLK2 or D3/Clk3)!

If you are comfortable with a bit of asynchronous logic, you could build the functio9n from these equations and a single D-FF:
FF clock: ClK_FF = (Clk1 + CLK2 + CLK3) delayed by xx ns
FF data: Din_FF = (Clk1*D1) + (Clk2*D2) + (CLK3*D3)
Where:
+ = logical OR
* = logical AND
xx ns = delay (e.g. using an RC delay element) where xx > delay of the logic gates for FF_Data + Setup-Time of the D-FF

This should work in the following manner:
Din_FF is the state of the data lien associated with the active clock (1*D)=D. The state of the data lines where the clock is inactive is ignored (0*D)=0.
This state is latched into the D-FF by the combined clock signal.

As long as you can ensure that only one clock is active a a time, this will work. It will fail, however, as soon as two or more clock signals are active (1) at the same time because Din_FF then represents the combination of more than one data input. But this configuration is illegal acc. to your post #14.

If you are not comfortable with asynchronously clocking the D-FF, you could synchronize the whole thing using a master clock (which needs to have a frquency considerably higher than the individual clocks) and a few additional flip-flops to put all signals in sync.

19. ### LateBlt

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Sep 14, 2015
Well, there are 3 signals used to trigger the input (Clk1, Clk2, and Clk3), so hopefully the user (or the program driving the circuit) knows which of those 3 it activated. As long as you know which of those 3 you used, you'll know whether the input data came from D1, D2, or D3.

I think your solution is pretty straightforward. It only uses a few additional OR and AND operations, which is not too bad, and then a reasonable timing delay, which is not too much of a problem since the flip-flops will of course be driven by a clock which has some inherent time gap between clock pulses anyway. The only tricky bit is figuring out exactly what the timing is, but timing is always an inherent component in any digital system which I'd have to end up reckoning anyway. Thanks for your response! I think it simplifies things pretty well.

20. ### AnalogKid

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Jun 10, 2015
The description in post #14 looks like one normal D ff with a 3-in or in the D input and a 3-in OR on the clock input. Most of the world's problems can be solved with a CPLD, but that's overkill for this.

ak